Lines Matching +full:0 +full:xfffb0000
2 .psize 0
14 0x000 - 0x050 TX#0 0x050 - 0x140 RX#0
15 0x140 - 0x190 TX#1 0x190 - 0x280 RX#1
16 0x280 - 0x2D0 TX#2 0x2D0 - 0x3C0 RX#2
17 0x3C0 - 0x410 TX#3 0x410 - 0x500 RX#3
43 PCI9060_VECTOR = 0x0000006C
44 CPM_IRQ_BASE = 0x40
46 SCC1_VECTOR = (CPM_IRQ_BASE + 0x1E) * 4
47 SCC2_VECTOR = (CPM_IRQ_BASE + 0x1D) * 4
48 SCC3_VECTOR = (CPM_IRQ_BASE + 0x1C) * 4
49 SCC4_VECTOR = (CPM_IRQ_BASE + 0x1B) * 4
53 PITR_CONST = 0x100 + 16 // 1 Hz timer
55 MBAR = 0x0003FF00
57 VALUE_WINDOW = 0x40000000
58 ORDER_WINDOW = 0xC0000000
60 PLX = 0xFFF90000
62 CSRA = 0xFFFB0000
63 CSRB = 0xFFFB0002
64 CSRC = 0xFFFB0004
65 CSRD = 0xFFFB0006
66 STATUS_CABLE_LL = 0x2000
67 STATUS_CABLE_DTR = 0x1000
69 DPRBASE = 0xFFFC0000
71 SCC1_BASE = DPRBASE + 0xC00
72 MISC_BASE = DPRBASE + 0xCB0
73 SCC2_BASE = DPRBASE + 0xD00
74 SCC3_BASE = DPRBASE + 0xE00
75 SCC4_BASE = DPRBASE + 0xF00
79 SCC_RBASE = 0 // 16-bit RxBD base address
84 SCC_C_MASK = 0x34 // 32-bit CRC constant
85 SCC_C_PRES = 0x38 // 32-bit CRC preset
86 SCC_MFLR = 0x46 // 16-bit max Rx frame length (without flags)
88 REGBASE = DPRBASE + 0x1000
89 PICR = REGBASE + 0x026 // 16-bit periodic irq control
90 PITR = REGBASE + 0x02A // 16-bit periodic irq timing
91 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options
92 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
93 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
94 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
95 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap
96 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap
97 PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap
98 PADAT = REGBASE + 0x556 // 16-bit PortA data register
100 PCDIR = REGBASE + 0x560 // 16-bit PortC data direction bitmap
101 PCPAR = REGBASE + 0x562 // 16-bit PortC pin assignment bitmap
102 PCSO = REGBASE + 0x564 // 16-bit PortC special options
103 PCDAT = REGBASE + 0x566 // 16-bit PortC data register
104 PCINT = REGBASE + 0x568 // 16-bit PortC interrupt control
105 CR = REGBASE + 0x5C0 // 16-bit Command register
107 SCC1_REGS = REGBASE + 0x600
108 SCC2_REGS = REGBASE + 0x620
109 SCC3_REGS = REGBASE + 0x640
110 SCC4_REGS = REGBASE + 0x660
111 SICR = REGBASE + 0x6EC // 32-bit SI clock route
114 SCC_GSMR_L = 0x00 // 32 bits
115 SCC_GSMR_H = 0x04 // 32 bits
116 SCC_PSMR = 0x08 // 16 bits
117 SCC_TODR = 0x0C // 16 bits
118 SCC_DSR = 0x0E // 16 bits
119 SCC_SCCE = 0x10 // 16 bits
120 SCC_SCCM = 0x14 // 16 bits
121 SCC_SCCS = 0x17 // 8 bits
126 andl #0xFFFFFFFC, \len // always copy n * 4 bytes
130 movel #0x0103, PLX_DMA_CMD_STS // start channel 0 transfer
136 andl #0xFFFFFFFC, \len // always copy n * 4 bytes
140 movel #0x0301, PLX_DMA_CMD_STS // start channel 1 transfer
148 movel \len, %d7 // bits 0 and 1
151 beq 99f // only 0 - 3 bytes
159 99: btstl #0, \len
179 99: btstl #0, CR
192 ch_status_addr: .long 0, 0, 0, 0
193 rx_descs_addr: .long 0
198 andl #0xF00007FF, %d0 // mask AMxx bits
199 orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size
220 movel #0x78000000, CIMR // only SCCx IRQs from CPM
225 movel #0xD41F40 + (CPM_IRQ_LEVEL << 13), CICR
226 movel #0x543, PLX_DMA_0_MODE // 32-bit, Ready, Burst, IRQ
227 movel #0x543, PLX_DMA_1_MODE
228 movel #0x0, PLX_DMA_0_DESC // from PCI to local
229 movel #0x8, PLX_DMA_1_DESC // from local to PCI
230 movel #0x101, PLX_DMA_CMD_STS // enable both DMA channels
232 orl #0x000F0300, PLX_INTERRUPT_CS
241 movew #0xFFFF, PAPAR // all pins are clocks/data
254 stop #0x2200 // supervisor + IRQ level 2
255 movew #0x2700, %sr // disable IRQs again
320 movel #0x18000000, %d3 // D3 = initial TX BD flags: Int + Last
337 movel #0x90000000, (%a1)+ // RX flags + length
342 movel #0xB0000000, (%a1)+ // Final RX flags + length
349 movel #0xFFFF, SCC_SCCE(%a2) // clear status bits
350 movel #0x0000, SCC_SCCM(%a2) // interrupt mask
356 moveb #0x8, SCC_RFCR(%a1) // Intel mode, 1000
357 moveb #0x8, SCC_TFCR(%a1)
363 movel #0xF0B8, SCC_C_MASK(%a1)
364 movel #0xFFFF, SCC_C_PRES(%a1)
372 movew #0x0800, SCC_PSMR(%a2) // CRC32-CCITT
373 movel #0xDEBB20E3, SCC_C_MASK(%a1)
374 movel #0xFFFFFFFF, SCC_C_PRES(%a1)
382 clrw SCC_PSMR(%a2) // CRC16-CCITT preset 0
383 movel #0xF0B8, SCC_C_MASK(%a1)
392 movew #0x0800, SCC_PSMR(%a2) // CRC32-CCITT preset 0
393 movel #0xDEBB20E3, SCC_C_MASK(%a1)
401 movel #0xF0B8, SCC_C_MASK(%a1)
402 movel #0xFFFF, SCC_C_PRES(%a1)
403 movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC
407 movel #0x00000003, SCC_GSMR_H(%a2) // RTSM
410 movel #0x10040900, SCC_GSMR_L(%a2) // NRZI: TCI Tend RECN+TENC=1
414 movel #0x10040000, SCC_GSMR_L(%a2) // NRZ: TCI Tend RECN+TENC=0
424 movew #0x001F, SCC_SCCM(%a2) // TXE RXF BSY TXB RXB interrupts
425 orl #0x00000030, SCC_GSMR_L(%a2) // enable SCC
435 andl #0xFFFFFFCF, SCC_GSMR_L(%a0) // Disable ENT and ENR
501 andw #0x0CBC, %d2 // mask status bits
502 cmpw #0x0C00, %d2 // correct frame
536 andw #0xF000, (%d1) // clear CM and error bits
612 stop #0x2200 // enable PCI9060 interrupts
613 movew #0x2700, %sr // disable interrupts again
623 stop #0x2200 // enable PCI9060 interrupts
624 movew #0x2700, %sr // disable interrupts again
647 movel #0x0909, PLX_DMA_CMD_STS // clear DMA ch #0 and #1 interrupts
655 orl #0, SCC1_REGS + SCC_SCCE; // confirm SCC events
657 movel #0x40000000, CISR
661 orl #0, SCC2_REGS + SCC_SCCE; // confirm SCC events
663 movel #0x20000000, CISR
667 orl #0, SCC3_REGS + SCC_SCCE; // confirm SCC events
669 movel #0x10000000, CISR
673 orl #0, SCC4_REGS + SCC_SCCE; // confirm SCC events
675 movel #0x08000000, CISR
696 andl #0xE7, %d1 // PM and cable sense bits (no DCE bit)
699 movew #0x0E08, %d1
705 movew #0x0408, %d1
711 movew #0x0208, %d1
717 movew #0x0D08, %d1
721 movew #0x0008, %d1 // D1 = disable everything
722 movew #0x80E7, %d2 // D2 = input mask: ignore DSR
727 andw #0x3000, %d2 // D2 = requested LL and DTR bits
729 movew #0x80FF, %d2 // D2 = input mask: include DSR
780 movel #0x12345678, %d1 // D1 = test value
795 eorl #0xFFFFFFFF, %d1
808 subl #0x10000, %d1
809 cmpl #0xFFFFFFFF, %d1
816 subl #0x10000, %d0
817 cmpl #0xFFFFFFFF, %d0
866 .long 0x0000002C, 0x00003E00, 0x002C0000, 0x3E000000
868 .long 0x0000002D, 0x00003F00, 0x002D0000, 0x3F000000
870 .long 0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000
872 .word 0x020, 0, 0x080, 0, 0x200, 0, 0x800
881 channel_stats: .long 0
883 tx_in: .long 0, 0, 0, 0 // transmitted
884 tx_out: .long 0, 0, 0, 0 // received from host for transmission
885 tx_count: .long 0, 0, 0, 0 // currently in transmit queue
887 rx_in: .long 0, 0, 0, 0 // received from port
888 rx_out: .long 0 // transmitted to host
889 parity_bytes: .word 0, 0, 0, 0, 0, 0, 0 // only 4 words are used
891 csr_output: .word 0
892 old_csr_output: .word 0, 0, 0, 0, 0, 0, 0