Lines Matching +full:rx +full:- +full:input +full:- +full:m

1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
20 #define WCRM   0x05		/* Wait Control M */
42 /* MSCI channel (port) 0 registers - offset 0x20
43    MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL   0x00		/* TX/RX buffer L */ 
49 #define TRBH   0x01		/* TX/RX buffer H */ 
68 #define RXS    0x16		/* RX Clock Source */
72 #define RRC    0x1A		/* RX Ready Control */ 
77 /* Timer channel 0 (port 0 RX) registers - offset 0x60
78    Timer channel 1 (port 0 TX) registers - offset 0x68
79    Timer channel 2 (port 1 RX) registers - offset 0x70
80    Timer channel 3 (port 1 TX) registers - offset 0x78
88 #define TCNTL  0x00		/* Up-counter L */
89 #define TCNTH  0x01		/* Up-counter H */
97 /* DMA channel 0 (port 0 RX) registers - offset 0x80
98    DMA channel 1 (port 0 TX) registers - offset 0xA0
99    DMA channel 2 (port 1 RX) registers - offset 0xC0
100    DMA channel 3 (port 1 TX) registers - offset 0xE0
112 #define DARL   0x00		/* RX Destination Addr L (single block) */
113 #define DARH   0x01		/* RX Destination Addr H (single block) */
114 #define DARB   0x02		/* RX Destination Addr B (single block) */
126 #define BFLL   0x0C		/* RX Receive Buffer Length L (chained block)*/
127 #define BFLH   0x0D		/* RX Receive Buffer Length H (chained block)*/
156 	u8 unused;		/* pads to 2-byte boundary */
175 #define DIR_EOME      0x40      /* Frame Transfer Completed (chained-block) */
176 #define DIR_BOFE      0x20      /* Buffer Overflow/Underflow (chained-block)*/
177 #define DIR_COFE      0x10      /* Counter Overflow (chained-block) */
181 #define DSR_EOM       0x40      /* Frame Transfer Completed (chained-block) */
182 #define DSR_BOF       0x20      /* Buffer Overflow/Underflow (chained-block)*/
183 #define DSR_COF       0x10      /* Counter Overflow (chained-block) */
195 #define MD0_HDLC      0x80	/* Bit-sync HDLC mode */
197 #define MD0_CRC_CCITT 0x02	/* CCITT CRC instead of CRC-16 */
198 #define MD0_CRC_PR1   0x01	/* Initial all-ones instead of all-zeros */
218 #define ST0_RXRDY     0x01	/* RX ready */
223 #define ST3_CTS       0x08	/* modem input - /CTS */
224 #define ST3_DCD       0x04	/* modem input - /DCD */
227 #define IE0_RXINTA    0x40	/* RX INT A MSCI interrupt enable */
234 /* TX and RX Clock Source - RXS and TXS */
236 #define CLK_LINE_RX   0x00	/* TX/RX clock line input */
237 #define CLK_LINE_TX   0x00	/* TX/RX line input */
240 #define CLK_RXCLK_TX  0x60	/* TX clock from RX clock */