Lines Matching +full:tx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
11 /* Tx command words */
17 #define TX_CMD_B_CSUM_ENABLE (0x00004000) /* TX Checksum Enable */
38 /* SCSRs - System Control and Status Registers */
53 #define INT_STS_TX_STOP_ (0x00020000) /* TX Stopped */
57 #define INT_STS_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
58 #define INT_STS_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
69 #define TX_CFG_ON_ (0x00000004) /* Transmitter Enable */
79 #define HW_CFG_IME_ (0x00000080) /* Internal MII Visi. Enable */
85 #define HW_CFG_BCE_ (0x00000002) /* Burst Cap Enable */
94 #define TX_FIFO_INF_FREE_ (0x0000FFFF) /* TX Data FIFO Free Space */
107 #define PM_CTL_WOL_EN_ (0x00000008) /* Wake On Lan Enable */
108 #define PM_CTL_ED_EN_ (0x00000004) /* Energy Detect Enable */
145 #define E2P_CMD_EWEN_ (0x20000000) /* Erase/Write Enable */
167 #define STRAP_STATUS_PWR_SEL_ (0x00000020) /* Device self-powered */
168 #define STRAP_STATUS_AMDIX_EN_ (0x00000010) /* Auto-MDIX Enabled */
169 #define STRAP_STATUS_PORT_SWAP_ (0x00000008) /* USBD+/USBD- Swapped */
189 /* General Purpose IO Wake Enable and Polarity Register */
194 #define INT_EP_CTL_INTEP_ (0x80000000) /* Always TX Interrupt PKT */
197 #define INT_EP_CTL_TX_STOP_ (0x00020000) /* TX Stopped */
200 #define INT_EP_CTL_TXE_ (0x00004000) /* TX Error */
201 #define INT_EP_CTL_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
202 #define INT_EP_CTL_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
204 #define INT_EP_CTL_GPIOS_ (0x000007FF) /* GPIOs Interrupt Enable */
209 /* MAC CSRs - MAC Control and Status Registers */
228 #define MAC_CR_TXEN_ (0x00000008) /* Transmitter Enable */
229 #define MAC_CR_RXEN_ (0x00000004) /* Receiver Enable */
256 #define FLOW_FCEN_ (0x00000002) /* Flow Control Enable */
273 #define WUCSR_GUE_ (0x00000200) /* Global Unicast Enable */
276 #define WUCSR_WAKE_EN_ (0x00000004) /* Wakeup Frame Enable */
277 #define WUCSR_MPEN_ (0x00000002) /* Magic Packet Enable */
281 #define Tx_COE_EN_ (0x00010000) /* TX Csum Offload Enable */
283 #define Rx_COE_EN_ (0x00000001) /* RX Csum Offload Enable */
285 /* Vendor-specific PHY Definitions (via MII access) */
344 #define INT_ENP_TX_STOP_ ((u32)BIT(17)) /* TX Stopped */
347 #define INT_ENP_TXE_ ((u32)BIT(14)) /* TX Error */
348 #define INT_ENP_TDFU_ ((u32)BIT(13)) /* TX FIFO Underrun */
349 #define INT_ENP_TDFO_ ((u32)BIT(12)) /* TX FIFO Overrun */