Lines Matching +full:tx +full:- +full:csum +full:- +full:limit

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  * Copyright (C) 2007-2008 SMSC
11 /* Tx command words */
17 #define TX_CMD_B_CSUM_ENABLE	(0x00004000)	/* TX Checksum Enable */
38 /* SCSRs - System Control and Status Registers */
53 #define INT_STS_TX_STOP_	(0x00020000)	/* TX Stopped */
57 #define INT_STS_TDFU_		(0x00002000)	/* TX Data FIFO Underrun */
58 #define INT_STS_TDFO_		(0x00001000)	/* TX Data FIFO Overrun */
94 #define TX_FIFO_INF_FREE_	(0x0000FFFF)	/* TX Data FIFO Free Space */
167 #define	STRAP_STATUS_PWR_SEL_		(0x00000020) /* Device self-powered */
168 #define	STRAP_STATUS_AMDIX_EN_		(0x00000010) /* Auto-MDIX Enabled */
169 #define	STRAP_STATUS_PORT_SWAP_		(0x00000008) /* USBD+/USBD- Swapped */
194 #define INT_EP_CTL_INTEP_	(0x80000000)	/* Always TX Interrupt PKT */
197 #define INT_EP_CTL_TX_STOP_	(0x00020000)	/* TX Stopped */
200 #define INT_EP_CTL_TXE_		(0x00004000)	/* TX Error */
201 #define INT_EP_CTL_TDFU_	(0x00002000)	/* TX Data FIFO Underrun */
202 #define INT_EP_CTL_TDFO_	(0x00001000)	/* TX Data FIFO Overrun */
209 /* MAC CSRs - MAC Control and Status Registers */
226 #define MAC_CR_BOLMT_MASK	(0x000000C0)	/* BackOff Limit */
281 #define Tx_COE_EN_		(0x00010000)	/* TX Csum Offload Enable */
282 #define Rx_COE_MODE_		(0x00000002)	/* RX Csum Offload Mode */
283 #define Rx_COE_EN_		(0x00000001)	/* RX Csum Offload Enable */
285 /* Vendor-specific PHY Definitions (via MII access) */
344 #define INT_ENP_TX_STOP_		((u32)BIT(17))	/* TX Stopped */
347 #define INT_ENP_TXE_			((u32)BIT(14))	/* TX Error */
348 #define INT_ENP_TDFU_			((u32)BIT(13))	/* TX FIFO Underrun */
349 #define INT_ENP_TDFO_			((u32)BIT(12))	/* TX FIFO Overrun */