Lines Matching +full:auto +full:- +full:flow +full:- +full:control

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
82 #define HW_CFG_ETC_		(0x00000010)	/* EEPROM Timeout Control */
96 /* Power Management Control Register */
124 /* Automatic Flow Control Configuration Register */
126 #define AFC_CFG_HI_		(0x00FF0000)	/* Auto Flow Ctrl High Level */
127 #define AFC_CFG_LO_		(0x0000FF00)	/* Auto Flow Ctrl Low Level */
129 #define AFC_CFG_FC_MULT_	(0x00000008)	/* Flow Ctrl on Mcast Frame */
130 #define AFC_CFG_FC_BRD_		(0x00000004)	/* Flow Ctrl on Bcast Frame */
131 #define AFC_CFG_FC_ADD_		(0x00000002)	/* Flow Ctrl on Addr. Decode */
132 #define AFC_CFG_FC_ANY_		(0x00000001)	/* Flow Ctrl on Any Frame */
167 #define	STRAP_STATUS_PWR_SEL_		(0x00000020) /* Device self-powered */
168 #define	STRAP_STATUS_AMDIX_EN_		(0x00000010) /* Auto-MDIX Enabled */
169 #define	STRAP_STATUS_PORT_SWAP_		(0x00000008) /* USBD+/USBD- Swapped */
192 /* Interrupt Endpoint Control Register */
209 /* MAC CSRs - MAC Control and Status Registers */
210 /* MAC Control Register */
222 #define MAC_CR_LCOLL_		(0x00001000)	/* Late Collision Control */
252 /* Flow Control Register */
253 #define FLOW			(0x11C)  macro
255 #define FLOW_FCPASS_		(0x00000004)	/* Pass Control Frames */
256 #define FLOW_FCEN_		(0x00000002)	/* Flow Control Enable */
257 #define FLOW_FCBSY_		(0x00000001)	/* Flow Control Busy */
270 /* Wake Up Control and Status Register */
279 /* Checksum Offload Engine Control Register */
285 /* Vendor-specific PHY Definitions (via MII access) */
303 /* Mode Control/Status Register */
308 /* Control/Status Indication Register */
329 /* PHY Special Control/Status Register */