Lines Matching +full:10 +full:- +full:gigabit
1 // SPDX-License-Identifier: GPL-2.0+
34 #define RTL8211E_INER_LINK_STATUS BIT(10)
125 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
126 * is set, they cannot be accessed by C45-over-C22.
139 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
219 struct device *dev = &phydev->mdio.dev; in rtl821x_probe()
221 u32 phy_id = phydev->drv->phy_id; in rtl821x_probe()
226 return -ENOMEM; in rtl821x_probe()
228 priv->clk = devm_clk_get_optional_enabled(dev, NULL); in rtl821x_probe()
229 if (IS_ERR(priv->clk)) in rtl821x_probe()
230 return dev_err_probe(dev, PTR_ERR(priv->clk), in rtl821x_probe()
237 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); in rtl821x_probe()
238 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) in rtl821x_probe()
239 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; in rtl821x_probe()
241 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); in rtl821x_probe()
242 if (priv->has_phycr2) { in rtl821x_probe()
247 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; in rtl821x_probe()
248 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) in rtl821x_probe()
249 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; in rtl821x_probe()
252 phydev->priv = priv; in rtl821x_probe()
259 struct device *dev = &phydev->mdio.dev; in rtl8211f_probe()
276 if (device_property_read_bool(dev, "wakeup-source") && in rtl8211f_probe()
279 devm_pm_set_wake_irq(dev, phydev->irq); in rtl8211f_probe()
317 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8201_config_intr()
340 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211b_config_intr()
362 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211e_config_intr()
382 struct rtl821x_priv *priv = phydev->priv; in rtl8211f_config_intr()
386 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211f_config_intr()
394 priv->iner = val; in rtl8211f_config_intr()
396 priv->iner = val = 0; in rtl8211f_config_intr()
465 pm_wakeup_event(&phydev->mdio.dev, 0); in rtl8211f_handle_interrupt()
479 if (!device_can_wakeup(&dev->mdio.dev)) { in rtl8211f_get_wol()
480 wol->supported = 0; in rtl8211f_get_wol()
484 wol->supported = WAKE_MAGIC; in rtl8211f_get_wol()
491 wol->wolopts = WAKE_MAGIC; in rtl8211f_get_wol()
496 const u8 *mac_addr = dev->attached_dev->dev_addr; in rtl8211f_set_wol()
499 if (!device_can_wakeup(&dev->mdio.dev)) in rtl8211f_set_wol()
500 return -EOPNOTSUPP; in rtl8211f_set_wol()
506 if (wol->wolopts & WAKE_MAGIC) { in rtl8211f_set_wol()
528 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC)); in rtl8211f_set_wol()
545 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { in rtl8211_config_aneg()
558 /* RTL8211C has an issue when operating in Gigabit slave mode */ in rtl8211c_config_init()
565 struct rtl821x_priv *priv = phydev->priv; in rtl8211f_config_init()
566 struct device *dev = &phydev->mdio.dev; in rtl8211f_config_init()
572 priv->phycr1); in rtl8211f_config_init()
579 switch (phydev->interface) { in rtl8211f_config_init()
612 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", in rtl8211f_config_init()
616 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", in rtl8211f_config_init()
628 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", in rtl8211f_config_init()
632 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", in rtl8211f_config_init()
636 if (!priv->has_phycr2) in rtl8211f_config_init()
639 /* Disable PHY-mode EEE so LPI is passed to the MAC */ in rtl8211f_config_init()
647 priv->phycr2); in rtl8211f_config_init()
659 struct rtl821x_priv *priv = phydev->priv; in rtl821x_suspend()
662 if (!phydev->wol_enabled) { in rtl821x_suspend()
668 clk_disable_unprepare(priv->clk); in rtl821x_suspend()
687 if (device_may_wakeup(&phydev->mdio.dev)) { in rtl8211f_suspend()
722 struct rtl821x_priv *priv = phydev->priv; in rtl821x_resume()
725 if (!phydev->wol_enabled) in rtl821x_resume()
726 clk_prepare_enable(priv->clk); in rtl821x_resume()
739 struct rtl821x_priv *priv = phydev->priv; in rtl8211f_resume()
749 if (device_may_wakeup(&phydev->mdio.dev)) in rtl8211f_resume()
750 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner); in rtl8211f_resume()
766 * - Link: Configurable subset of 10/100/1000 link rates in rtl8211x_led_hw_is_supported()
767 * - Active: Blink on activity, RX or TX is not differentiated in rtl8211x_led_hw_is_supported()
769 * - A: Link and Active indication at configurable, but matching, in rtl8211x_led_hw_is_supported()
770 * subset of 10/100/1000 link rates in rtl8211x_led_hw_is_supported()
771 * - B: Link indication at configurable subset of 10/100/1000 link in rtl8211x_led_hw_is_supported()
772 * rates and Active indication always at all three 10+100+1000 in rtl8211x_led_hw_is_supported()
780 return -EINVAL; in rtl8211x_led_hw_is_supported()
784 return -EOPNOTSUPP; in rtl8211x_led_hw_is_supported()
788 return -EOPNOTSUPP; in rtl8211x_led_hw_is_supported()
799 return -EINVAL; in rtl8211f_led_hw_control_get()
838 return -EINVAL; in rtl8211f_led_hw_control_set()
873 return -EINVAL; in rtl8211e_led_hw_control_get()
921 return -EINVAL; in rtl8211e_led_hw_control_set()
960 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ in rtl8211e_config_init()
961 switch (phydev->interface) { in rtl8211e_config_init()
985 * 10:0 = Test && debug settings reserved by realtek in rtl8211e_config_init()
1013 dev_err(&phydev->mdio.dev, in rtl8366rb_config_init()
1028 phydev->duplex = DUPLEX_FULL; in rtlgen_decode_physr()
1030 phydev->duplex = DUPLEX_HALF; in rtlgen_decode_physr()
1034 phydev->speed = SPEED_10; in rtlgen_decode_physr()
1037 phydev->speed = SPEED_100; in rtlgen_decode_physr()
1040 phydev->speed = SPEED_1000; in rtlgen_decode_physr()
1043 phydev->speed = SPEED_10000; in rtlgen_decode_physr()
1046 phydev->speed = SPEED_2500; in rtlgen_decode_physr()
1049 phydev->speed = SPEED_5000; in rtlgen_decode_physr()
1059 if (phydev->speed >= 1000) { in rtlgen_decode_physr()
1061 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in rtlgen_decode_physr()
1063 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in rtlgen_decode_physr()
1065 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; in rtlgen_decode_physr()
1077 if (!phydev->link) in rtlgen_read_status()
1091 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); in rtlgen_read_vend2()
1096 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, in rtlgen_write_vend2()
1113 ret = -EOPNOTSUPP; in rtlgen_read_mmd()
1128 ret = -EOPNOTSUPP; in rtlgen_write_mmd()
1137 if (ret != -EOPNOTSUPP) in rtl822x_read_mmd()
1155 if (ret != -EOPNOTSUPP) in rtl822x_write_mmd()
1167 phydev->phy_id != RTL_GENERIC_PHYID) in rtl822x_probe()
1180 phydev->host_interfaces) || in rtl822x_set_serdes_option_mode()
1181 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; in rtl822x_set_serdes_option_mode()
1184 phydev->host_interfaces) || in rtl822x_set_serdes_option_mode()
1185 phydev->interface == PHY_INTERFACE_MODE_SGMII; in rtl822x_set_serdes_option_mode()
1188 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, in rtl822x_set_serdes_option_mode()
1190 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, in rtl822x_set_serdes_option_mode()
1199 phydev->rate_matching = RATE_MATCH_PAUSE; in rtl822x_set_serdes_option_mode()
1202 phydev->rate_matching = RATE_MATCH_NONE; in rtl822x_set_serdes_option_mode()
1248 /* Only rate matching at 2500base-x */ in rtl822xb_get_rate_matching()
1273 phydev->supported, val & MDIO_PMA_SPEED_2_5G); in rtl822x_get_features()
1275 phydev->supported, val & MDIO_PMA_SPEED_5G); in rtl822x_get_features()
1277 phydev->supported, val & MDIO_SPEED_10G); in rtl822x_get_features()
1286 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_config_aneg()
1287 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in rtl822x_config_aneg()
1304 if (!phydev->link) in rtl822xb_update_interface()
1314 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in rtl822xb_update_interface()
1317 phydev->interface = PHY_INTERFACE_MODE_SGMII; in rtl822xb_update_interface()
1326 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in rtl822x_read_status()
1332 if (phydev->autoneg == AUTONEG_DISABLE || in rtl822x_read_status()
1333 !phydev->autoneg_complete) in rtl822x_read_status()
1340 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); in rtl822x_read_status()
1361 phydev->supported); in rtl822x_c45_get_features()
1371 if (phydev->autoneg == AUTONEG_DISABLE) in rtl822x_c45_config_aneg()
1380 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in rtl822x_c45_config_aneg()
1399 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { in rtl822x_c45_read_status()
1407 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in rtl822x_c45_read_status()
1413 if (!phydev->link) { in rtl822x_c45_read_status()
1414 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in rtl822x_c45_read_status()
1468 * Check a MMD register which is known to be non-zero.
1487 return phydev->phy_id == RTL_GENERIC_PHYID && in rtlgen_match_phy_device()
1494 return phydev->phy_id == RTL_GENERIC_PHYID && in rtl8226_match_phy_device()
1502 if (phydev->is_c45) in rtlgen_is_c45_match()
1503 return is_c45 && (id == phydev->c45_ids.device_ids[1]); in rtlgen_is_c45_match()
1505 return !is_c45 && (id == phydev->phy_id); in rtlgen_is_c45_match()
1511 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); in rtl8221b_match_phy_device()
1541 if (phydev->is_c45) in rtl_internal_nbaset_match_phy_device()
1544 switch (phydev->phy_id) { in rtl_internal_nbaset_match_phy_device()
1585 phydev->autoneg = AUTONEG_DISABLE; in rtl9000a_config_init()
1586 phydev->speed = SPEED_100; in rtl9000a_config_init()
1587 phydev->duplex = DUPLEX_FULL; in rtl9000a_config_init()
1597 switch (phydev->master_slave_set) { in rtl9000a_config_aneg()
1608 return -EOPNOTSUPP; in rtl9000a_config_aneg()
1622 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in rtl9000a_read_status()
1623 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in rtl9000a_read_status()
1633 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in rtl9000a_read_status()
1635 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in rtl9000a_read_status()
1641 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in rtl9000a_read_status()
1643 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in rtl9000a_read_status()
1662 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl9000a_config_intr()
1725 .name = "RTL8211 Gigabit Ethernet",
1733 .name = "RTL8211B Gigabit Ethernet",
1744 .name = "RTL8211C Gigabit Ethernet",
1752 .name = "RTL8211DN Gigabit Ethernet",
1761 .name = "RTL8211E Gigabit Ethernet",
1774 .name = "RTL8211F Gigabit Ethernet",
1792 .name = "RTL8211F-VD Gigabit Ethernet",
1804 .name = "Generic FE-GE Realtek PHY",
1837 .name = "RTL8226-CG 2.5Gbps PHY",
1847 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1859 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1872 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1883 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1896 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)",
1918 .name = "Realtek Internal NBASE-T PHY",
1940 .name = "RTL8366RB Gigabit Ethernet",
1966 .name = "RTL8365MB-VC Gigabit Ethernet",
1974 .name = "RTL8366S Gigabit Ethernet",