Lines Matching refs:NXP_C45_REG_FIELD

195 #define NXP_C45_REG_FIELD(_reg, _devad, _offset, _size)	\  macro
1081 		NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 8, 6), },
1083 		NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 0, 6), },
1085 		NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 10, 6), },
1087 		NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 0, 10), },
1089 		NXP_C45_REG_FIELD(0x8350, MDIO_MMD_VEND1, 0, 16) },
1094 		NXP_C45_REG_FIELD(0xAFCE, MDIO_MMD_VEND1, 0, 6), },
1096 		NXP_C45_REG_FIELD(0xAFCF, MDIO_MMD_VEND1, 0, 6), },
1098 		NXP_C45_REG_FIELD(0xAFD0, MDIO_MMD_VEND1, 0, 9), },
1100 		NXP_C45_REG_FIELD(0xAFD1, MDIO_MMD_VEND1, 0, 9), },
1105 		NXP_C45_REG_FIELD(0x8351, MDIO_MMD_VEND1, 0, 14) },
1107 		NXP_C45_REG_FIELD(0xACA1, MDIO_MMD_VEND1, 0, 8), },
1109 		NXP_C45_REG_FIELD(0xACA0, MDIO_MMD_VEND1, 0, 16), },
1111 		NXP_C45_REG_FIELD(0xACA3, MDIO_MMD_VEND1, 0, 8), },
1113 		NXP_C45_REG_FIELD(0xACA2, MDIO_MMD_VEND1, 0, 16), },
1115 		NXP_C45_REG_FIELD(0xACA5, MDIO_MMD_VEND1, 0, 8), },
1117 		NXP_C45_REG_FIELD(0xACA4, MDIO_MMD_VEND1, 0, 16), },
1119 		NXP_C45_REG_FIELD(0xACA7, MDIO_MMD_VEND1, 0, 8), },
1121 		NXP_C45_REG_FIELD(0xACA6, MDIO_MMD_VEND1, 0, 16), },
1752 		NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 3, 1),
1754 		NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 2, 1),
1756 		NXP_C45_REG_FIELD(0x1115, MDIO_MMD_VEND1, 0, 1),
1758 		NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 2, 1),
1760 		NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 0, 1),
1772 		NXP_C45_REG_FIELD(0x1131, MDIO_MMD_VEND1, 0, 1),
1774 		NXP_C45_REG_FIELD(0x1132, MDIO_MMD_VEND1, 0, 1),
1776 		NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 0, 8),
1778 		NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 8, 4),
1780 		NXP_C45_REG_FIELD(0x114F, MDIO_MMD_VEND1, 0, 16),
1782 		NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 14, 2),
1784 		NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 12, 3),
1786 		NXP_C45_REG_FIELD(0x1150, MDIO_MMD_VEND1, 0, 16),
1788 		NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 0, 14),
1796 		NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 13, 1),
1798 		NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 0, 3),
1867 		NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 4, 1),
1869 		NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 5, 1),
1871 		NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 2, 1),
1873 		NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 1, 1),
1875 		NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 2, 1),
1887 		NXP_C45_REG_FIELD(0x900A, MDIO_MMD_VEND1, 1, 1),
1889 		NXP_C45_REG_FIELD(0x900C, MDIO_MMD_VEND1, 1, 1),
1891 		NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 8, 8),
1893 		NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 4, 4),
1895 		NXP_C45_REG_FIELD(0x9062, MDIO_MMD_VEND1, 0, 16),
1897 		NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 0, 2),
1899 		NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 2, 3),
1901 		NXP_C45_REG_FIELD(0x9063, MDIO_MMD_VEND1, 0, 16),
1903 		NXP_C45_REG_FIELD(0x9064, MDIO_MMD_VEND1, 0, 14),
1911 		NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 15, 1),
1913 		NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 0, 3),