Lines Matching full:phydev
289 void (*counters_enable)(struct phy_device *phydev);
293 void (*ptp_init)(struct phy_device *phydev);
294 void (*ptp_enable)(struct phy_device *phydev, bool enable);
295 void (*nmi_handler)(struct phy_device *phydev,
300 struct nxp_c45_phy_data *nxp_c45_get_data(struct phy_device *phydev)
302 return phydev->drv->driver_data;
306 struct nxp_c45_regmap *nxp_c45_get_regmap(struct phy_device *phydev)
308 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
313 static int nxp_c45_read_reg_field(struct phy_device *phydev,
320 phydev_err(phydev, "Trying to read a reg field of size 0.\n");
324 ret = phy_read_mmd(phydev, reg_field->devad, reg_field->reg);
337 static int nxp_c45_write_reg_field(struct phy_device *phydev,
345 phydev_err(phydev, "Trying to write a reg field of size 0.\n");
354 return phy_modify_mmd_changed(phydev, reg_field->devad,
358 static int nxp_c45_set_reg_field(struct phy_device *phydev,
362 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n");
366 return nxp_c45_write_reg_field(phydev, reg_field, 1);
369 static int nxp_c45_clear_reg_field(struct phy_device *phydev,
373 phydev_err(phydev, "Trying to set a reg field of size different than 1.\n");
377 return nxp_c45_write_reg_field(phydev, reg_field, 0);
380 static bool nxp_c45_poll_txts(struct phy_device *phydev)
382 return phydev->irq <= 0;
390 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
392 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_read);
393 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
395 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
397 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
399 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
422 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
424 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0,
426 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1,
428 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0,
430 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1,
432 nxp_c45_set_reg_field(priv->phydev, ®map->ltc_write);
452 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev);
464 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
472 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
517 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
519 extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
521 extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
523 extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
525 extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
527 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
533 static bool tja1120_extts_is_valid(struct phy_device *phydev)
538 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
548 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
549 struct phy_device *phydev = priv->phydev;
554 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
558 valid = tja1120_extts_is_valid(phydev);
566 phy_write_mmd(phydev, MDIO_MMD_VEND1,
568 valid = tja1120_extts_is_valid(phydev);
581 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
582 struct phy_device *phydev = priv->phydev;
585 nxp_c45_read_reg_field(phydev, ®map->domain_number);
587 nxp_c45_read_reg_field(phydev, ®map->msg_type);
589 nxp_c45_read_reg_field(phydev, ®map->sequence_id);
591 nxp_c45_read_reg_field(phydev, ®map->nsec_15_0);
593 nxp_c45_read_reg_field(phydev, ®map->nsec_29_16) << 16;
594 hwts->sec = nxp_c45_read_reg_field(phydev, ®map->sec_1_0);
595 hwts->sec |= nxp_c45_read_reg_field(phydev, ®map->sec_4_2) << 2;
605 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL,
607 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0);
618 static bool tja1120_egress_ts_is_valid(struct phy_device *phydev)
623 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S);
632 struct phy_device *phydev = priv->phydev;
638 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_END);
640 valid = tja1120_egress_ts_is_valid(phydev);
648 phy_write_mmd(phydev, MDIO_MMD_VEND1,
650 valid = tja1120_egress_ts_is_valid(phydev);
655 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S,
692 phydev_warn(priv->phydev,
700 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev);
701 bool poll_txts = nxp_c45_poll_txts(priv->phydev);
752 struct phy_device *phydev = priv->phydev;
754 phy_write_mmd(phydev, MDIO_MMD_VEND1,
761 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
762 struct phy_device *phydev = priv->phydev;
770 nxp_c45_clear_reg_field(priv->phydev,
772 nxp_c45_clear_reg_field(priv->phydev,
785 phydev_warn(phydev, "The period can be set only to 1 second.");
791 phydev_warn(phydev, "The start time is not configurable. Should be set to 0 seconds and 0 nanoseconds.");
797 phydev_warn(phydev, "The phase can be set only to 0 or 500000000 nanoseconds.");
802 nxp_c45_clear_reg_field(priv->phydev,
805 nxp_c45_set_reg_field(priv->phydev,
811 nxp_c45_set_reg_field(priv->phydev, ®map->pps_enable);
816 static void nxp_c45_set_rising_or_falling(struct phy_device *phydev,
820 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
824 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
828 static void nxp_c45_set_rising_and_falling(struct phy_device *phydev,
836 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
840 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
845 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
849 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
857 const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev);
878 nxp_c45_set_rising_and_falling(priv->phydev, extts);
880 nxp_c45_set_rising_or_falling(priv->phydev, extts);
962 &priv->phydev->mdio.dev);
985 if (nxp_c45_poll_txts(priv->phydev))
1021 struct phy_device *phydev = priv->phydev;
1027 data = nxp_c45_get_data(phydev);
1045 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1048 data->ptp_enable(phydev, true);
1050 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1053 data->ptp_enable(phydev, false);
1056 if (nxp_c45_poll_txts(priv->phydev))
1060 nxp_c45_set_reg_field(phydev, &data->regmap->irq_egr_ts_en);
1062 nxp_c45_clear_reg_field(phydev, &data->regmap->irq_egr_ts_en);
1132 static int nxp_c45_get_sset_count(struct phy_device *phydev)
1134 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
1139 static void nxp_c45_get_strings(struct phy_device *phydev, u8 *data)
1141 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
1142 size_t count = nxp_c45_get_sset_count(phydev);
1156 static void nxp_c45_get_stats(struct phy_device *phydev,
1159 const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
1160 size_t count = nxp_c45_get_sset_count(phydev);
1174 ret = nxp_c45_read_reg_field(phydev, reg_field);
1182 static int nxp_c45_config_enable(struct phy_device *phydev)
1184 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
1189 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL,
1191 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
1193 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL,
1199 static int nxp_c45_start_op(struct phy_device *phydev)
1201 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
1205 static int nxp_c45_config_intr(struct phy_device *phydev)
1209 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1210 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1215 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1219 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1224 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1228 static int tja1103_config_intr(struct phy_device *phydev)
1233 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_ALWAYS_ACCESSIBLE,
1238 return nxp_c45_config_intr(phydev);
1241 static int tja1120_config_intr(struct phy_device *phydev)
1245 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1246 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1250 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1256 return nxp_c45_config_intr(phydev);
1259 static irqreturn_t nxp_c45_handle_interrupt(struct phy_device *phydev)
1261 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev);
1262 struct nxp_c45_phy *priv = phydev->priv;
1267 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS);
1269 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK,
1271 phy_trigger_machine(phydev);
1275 irq = nxp_c45_read_reg_field(phydev, &data->regmap->irq_egr_ts_status);
1282 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1290 data->nmi_handler(phydev, &ret);
1291 nxp_c45_handle_macsec_interrupt(phydev, &ret);
1296 static int nxp_c45_soft_reset(struct phy_device *phydev)
1300 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
1307 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1313 static int nxp_c45_cable_test_start(struct phy_device *phydev)
1315 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev);
1317 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
1323 static int nxp_c45_cable_test_get_status(struct phy_device *phydev,
1326 const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev);
1330 ret = nxp_c45_read_reg_field(phydev, ®map->cable_test_valid);
1337 cable_test_result = nxp_c45_read_reg_field(phydev,
1342 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1346 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1350 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1354 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1358 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
1360 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1363 return nxp_c45_start_op(phydev);
1366 static int nxp_c45_get_sqi(struct phy_device *phydev)
1370 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY);
1379 static void tja1120_link_change_notify(struct phy_device *phydev)
1384 if (phydev->state == PHY_NOLINK) {
1385 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1387 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1392 static int nxp_c45_get_sqi_max(struct phy_device *phydev)
1397 static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay)
1400 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS);
1405 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS);
1412 static void nxp_c45_counters_enable(struct phy_device *phydev)
1414 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev);
1416 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER,
1419 data->counters_enable(phydev);
1422 static void nxp_c45_ptp_init(struct phy_device *phydev)
1424 const struct nxp_c45_phy_data *data = nxp_c45_get_data(phydev);
1426 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1429 nxp_c45_clear_reg_field(phydev, &data->regmap->ltc_lock_ctrl);
1431 data->ptp_init(phydev);
1445 static void nxp_c45_disable_delays(struct phy_device *phydev)
1447 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE);
1448 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE);
1451 static void nxp_c45_set_delays(struct phy_device *phydev)
1453 struct nxp_c45_phy *priv = phydev->priv;
1458 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1459 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1461 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
1464 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
1468 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1469 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
1471 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
1474 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
1479 static int nxp_c45_get_delays(struct phy_device *phydev)
1481 struct nxp_c45_phy *priv = phydev->priv;
1484 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1485 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1486 ret = device_property_read_u32(&phydev->mdio.dev,
1492 ret = nxp_c45_check_delay(phydev, priv->tx_delay);
1494 phydev_err(phydev,
1500 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1501 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
1502 ret = device_property_read_u32(&phydev->mdio.dev,
1508 ret = nxp_c45_check_delay(phydev, priv->rx_delay);
1510 phydev_err(phydev,
1519 static int nxp_c45_set_phy_mode(struct phy_device *phydev)
1521 struct nxp_c45_phy *priv = phydev->priv;
1525 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES);
1526 phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret);
1528 switch (phydev->interface) {
1531 phydev_err(phydev, "rgmii mode not supported\n");
1534 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1536 nxp_c45_disable_delays(phydev);
1542 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n");
1545 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1547 ret = nxp_c45_get_delays(phydev);
1551 nxp_c45_set_delays(phydev);
1555 phydev_err(phydev, "mii mode not supported\n");
1558 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1563 phydev_err(phydev, "rev-mii mode not supported\n");
1566 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1571 phydev_err(phydev, "rmii mode not supported\n");
1581 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1586 phydev_err(phydev, "sgmii mode not supported\n");
1589 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
1602 static void nxp_c45_tja1120_errata(struct phy_device *phydev)
1609 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
1619 phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1629 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
1630 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
1632 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
1633 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
1636 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
1638 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);
1639 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);
1641 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
1642 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
1648 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1651 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1658 static int nxp_c45_config_init(struct phy_device *phydev)
1662 ret = nxp_c45_config_enable(phydev);
1664 phydev_err(phydev, "Failed to enable config\n");
1671 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1);
1672 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2);
1674 if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4)))
1675 nxp_c45_tja1120_errata(phydev);
1677 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
1680 ret = nxp_c45_set_phy_mode(phydev);
1684 phydev->autoneg = AUTONEG_DISABLE;
1686 nxp_c45_counters_enable(phydev);
1687 nxp_c45_ptp_init(phydev);
1688 ret = nxp_c45_macsec_config_init(phydev);
1692 return nxp_c45_start_op(phydev);
1695 static int nxp_c45_get_features(struct phy_device *phydev)
1697 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
1698 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported);
1700 return genphy_c45_pma_read_abilities(phydev);
1703 static int nxp_c45_parse_dt(struct phy_device *phydev)
1705 struct device_node *node = phydev->mdio.dev.of_node;
1706 struct nxp_c45_phy *priv = phydev->priv;
1717 static int nxp_c45_probe(struct phy_device *phydev)
1725 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1732 priv->phydev = phydev;
1734 phydev->priv = priv;
1736 nxp_c45_parse_dt(phydev);
1740 phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1744 phydev_dbg(phydev, "the phy does not support PTP");
1754 phydev->mii_ts = &priv->mii_ts;
1758 phydev->default_timestamp = true;
1760 phydev_dbg(phydev, "PTP support not enabled even if the phy supports it");
1766 phydev_info(phydev, "the phy does not support MACsec\n");
1771 ret = nxp_c45_macsec_probe(phydev);
1772 phydev_dbg(phydev, "MACsec support enabled.");
1774 phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it");
1782 static void nxp_c45_remove(struct phy_device *phydev)
1784 struct nxp_c45_phy *priv = phydev->priv;
1791 nxp_c45_macsec_remove(phydev);
1794 static void tja1103_counters_enable(struct phy_device *phydev)
1796 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT,
1798 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT,
1800 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH,
1802 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH,
1806 static void tja1103_ptp_init(struct phy_device *phydev)
1808 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL,
1810 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
1814 static void tja1103_ptp_enable(struct phy_device *phydev, bool enable)
1817 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1821 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1826 static void tja1103_nmi_handler(struct phy_device *phydev,
1831 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1834 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1909 static void tja1120_counters_enable(struct phy_device *phydev)
1911 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD,
1913 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS,
1915 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG,
1919 static void tja1120_ptp_init(struct phy_device *phydev)
1921 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_RX_TS_INSRT_CTRL,
1923 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_VEND1_EXT_TS_MODE,
1925 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG,
1929 static void tja1120_ptp_enable(struct phy_device *phydev, bool enable)
1932 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1936 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1941 static void tja1120_nmi_handler(struct phy_device *phydev,
1946 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1949 phy_write_mmd(phydev, MDIO_MMD_VEND1,
1956 static int nxp_c45_macsec_ability(struct phy_device *phydev)
1961 phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1968 static int tja11xx_no_macsec_match_phy_device(struct phy_device *phydev,
1971 if (!phy_id_compare(phydev->phy_id, phydrv->phy_id,
1975 return !nxp_c45_macsec_ability(phydev);
1978 static int tja11xx_macsec_match_phy_device(struct phy_device *phydev,
1981 if (!phy_id_compare(phydev->phy_id, phydrv->phy_id,
1985 return nxp_c45_macsec_ability(phydev);