23 #define PHY_ID_TJA_1103			0x001BB010
25 #define PHY_ID_TJA_1120			0x001BB031
27 #define VEND1_DEVICE_ID3		0x0004
30 #define DEVICE_ID3_SAMPLE_TYPE_R	0x9
32 #define VEND1_DEVICE_CONTROL		0x0040
37 #define VEND1_DEVICE_CONFIG		0x0048
39 #define TJA1120_VEND1_EXT_TS_MODE	0x1012
41 #define TJA1120_GLOBAL_INFRA_IRQ_ACK	0x2C08
42 #define TJA1120_GLOBAL_INFRA_IRQ_EN	0x2C0A
43 #define TJA1120_GLOBAL_INFRA_IRQ_STATUS	0x2C0C
46 #define TJA1120_VEND1_PTP_TRIG_DATA_S	0x1070
48 #define TJA1120_EGRESS_TS_DATA_S	0x9060
49 #define TJA1120_EGRESS_TS_END		0x9067
50 #define TJA1120_TS_VALID		BIT(0)
53 #define VEND1_PHY_IRQ_ACK		0x80A0
54 #define VEND1_PHY_IRQ_EN		0x80A1
55 #define VEND1_PHY_IRQ_STATUS		0x80A2
58 #define VEND1_ALWAYS_ACCESSIBLE		0x801F
61 #define VEND1_PHY_CONTROL		0x8100
63 #define PHY_START_OP			BIT(0)
65 #define VEND1_PHY_CONFIG		0x8108
66 #define PHY_CONFIG_AUTO			BIT(0)
68 #define TJA1120_EPHY_RESETS		0x810A
71 #define VEND1_SIGNAL_QUALITY		0x8320
73 #define SQI_MASK			GENMASK(2, 0)
78 #define CABLE_TEST_OK			0x00
79 #define CABLE_TEST_SHORTED		0x01
80 #define CABLE_TEST_OPEN			0x02
81 #define CABLE_TEST_UNKNOWN		0x07
83 #define VEND1_PORT_CONTROL		0x8040
86 #define VEND1_PORT_ABILITIES		0x8046
90 #define VEND1_PORT_FUNC_IRQ_EN		0x807A
94 #define VEND1_PTP_IRQ_ACK		0x9008
97 #define VEND1_PORT_INFRA_CONTROL	0xAC00
100 #define VEND1_RXID			0xAFCC
101 #define VEND1_TXID			0xAFCD
104 #define VEND1_ABILITIES			0xAFC4
110 #define SGMII_ABILITY			BIT(0)
112 #define VEND1_MII_BASIC_CONFIG		0xAFC6
114 #define MII_BASIC_CONFIG_SGMII		0x9
115 #define MII_BASIC_CONFIG_RGMII		0x7
116 #define MII_BASIC_CONFIG_RMII		0x5
117 #define MII_BASIC_CONFIG_MII		0x4
119 #define VEND1_SGMII_BASIC_CONTROL	0xB000
122 #define VEND1_SYMBOL_ERROR_CNT_XTD	0x8351
124 #define VEND1_MONITOR_STATUS		0xAC80
126 #define VEND1_MONITOR_CONFIG		0xAC86
130 #define VEND1_SYMBOL_ERROR_COUNTER	0x8350
131 #define VEND1_LINK_DROP_COUNTER		0x8352
132 #define VEND1_LINK_LOSSES_AND_FAILURES	0x8353
133 #define VEND1_RX_PREAMBLE_COUNT		0xAFCE
134 #define VEND1_TX_PREAMBLE_COUNT		0xAFCF
135 #define VEND1_RX_IPG_LENGTH		0xAFD0
136 #define VEND1_TX_IPG_LENGTH		0xAFD1
139 #define VEND1_PTP_CONFIG		0x1102
142 #define TJA1120_SYNC_TRIG_FILTER	0x1010
149 #define VEND1_RX_TS_INSRT_CTRL		0x114D
150 #define TJA1103_RX_TS_INSRT_MODE2	0x02
152 #define TJA1120_RX_TS_INSRT_CTRL	0x9012
156 #define VEND1_EGR_RING_DATA_0		0x114E
157 #define VEND1_EGR_RING_CTRL		0x1154
161 #define RING_DONE			BIT(0)
163 #define TS_SEC_MASK			GENMASK(1, 0)
166 #define PHY_TEST_ENABLE			BIT(0)
168 #define VEND1_PORT_PTP_CONTROL		0x9000
174 #define EVENT_MSG_FILT_ALL		0x0F
175 #define EVENT_MSG_FILT_NONE		0x00
177 #define VEND1_GPIO_FUNC_CONFIG_BASE	0x2C40
180 #define GPIO_SIGNAL_PTP_TRIGGER		0x01
181 #define GPIO_SIGNAL_PPS_OUT		0x12
182 #define GPIO_DISABLE			0
194 #define PPM_TO_SUBNS_INC(ppb, ptp_clk_period) div_u64(GENMASK_ULL(31, 0) * \
199 #define TJA11XX_REVERSE_MODE		BIT(0)
319 	if (reg_field->size == 0) {  in nxp_c45_read_reg_field()
320 		phydev_err(phydev, "Trying to read a reg field of size 0.\n");  in nxp_c45_read_reg_field()
325 	if (ret < 0)  in nxp_c45_read_reg_field()
344 	if (reg_field->size == 0) {  in nxp_c45_write_reg_field()
345 		phydev_err(phydev, "Trying to write a reg field of size 0.\n");  in nxp_c45_write_reg_field()
377 	return nxp_c45_write_reg_field(phydev, reg_field, 0);  in nxp_c45_clear_reg_field()
382 	return phydev->irq <= 0;  in nxp_c45_poll_txts()
402 	return 0;  in _nxp_c45_ptp_gettimex64()
415 	return 0;  in nxp_c45_ptp_gettimex64()
434 	return 0;  in _nxp_c45_ptp_settime64()
446 	return 0;  in nxp_c45_ptp_settime64()
459 	inc = ppb >= 0;  in nxp_c45_ptp_adjfine()
477 	return 0;  in nxp_c45_ptp_adjfine()
492 	return 0;  in nxp_c45_ptp_adjtime()
687 		memset(&shhwtstamps, 0, sizeof(shhwtstamps));  in nxp_c45_process_txts()
726 		hwts.nsec = ts_raw & GENMASK(29, 0);  in nxp_c45_do_aux_work()
730 		NXP_C45_SKB_CB(skb)->header->reserved2 = 0;  in nxp_c45_do_aux_work()
736 		if (ts_valid && timespec64_compare(&ts, &priv->extts_ts) != 0) {  in nxp_c45_do_aux_work()
766 	if (pin < 0)  in nxp_c45_perout_enable()
777 		return 0;  in nxp_c45_perout_enable()
784 	if (perout->period.sec != 1 || perout->period.nsec != 0) {  in nxp_c45_perout_enable()
790 		if (perout->start.sec != 0 || perout->start.nsec != 0) {  in nxp_c45_perout_enable()
791 …phydev_warn(phydev, "The start time is not configurable. Should be set to 0 seconds and 0 nanoseco…  in nxp_c45_perout_enable()
795 		if (perout->phase.nsec != 0 &&  in nxp_c45_perout_enable()
797 			phydev_warn(phydev, "The phase can be set only to 0 or 500000000 nanoseconds.");  in nxp_c45_perout_enable()
801 		if (perout->phase.nsec == 0)  in nxp_c45_perout_enable()
813 	return 0;  in nxp_c45_perout_enable()
867 	if (pin < 0)  in nxp_c45_extts_enable()
874 		return 0;  in nxp_c45_extts_enable()
885 	ptp_schedule_worker(priv->ptp_clock, 0);  in nxp_c45_extts_enable()
887 	return 0;  in nxp_c45_extts_enable()
906 	{ "nxp_c45_gpio0", 0, PTP_PF_NONE},
935 	return 0;  in nxp_c45_ptp_verify_pin()
970 	return 0;  in nxp_c45_init_ptp_clock()
986 			ptp_schedule_worker(priv->ptp_clock, 0);  in nxp_c45_txtstamp()
1010 	ptp_schedule_worker(priv->ptp_clock, 0);  in nxp_c45_rxtstamp()
1024 	if (cfg->tx_type < 0 || cfg->tx_type > HWTSTAMP_TX_ON)  in nxp_c45_hwtstamp()
1032 		priv->hwts_rx = 0;  in nxp_c45_hwtstamp()
1065 	return 0;  in nxp_c45_hwtstamp()
1084 	return 0;  in nxp_c45_ts_info()
1089 		NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 8, 6), },
1091 		NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 0, 6), },
1093 		NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 10, 6), },
1095 		NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 0, 10), },
1097 		NXP_C45_REG_FIELD(0x8350, MDIO_MMD_VEND1, 0, 16) },
1102 		NXP_C45_REG_FIELD(0xAFCE, MDIO_MMD_VEND1, 0, 6), },
1104 		NXP_C45_REG_FIELD(0xAFCF, MDIO_MMD_VEND1, 0, 6), },
1106 		NXP_C45_REG_FIELD(0xAFD0, MDIO_MMD_VEND1, 0, 9), },
1108 		NXP_C45_REG_FIELD(0xAFD1, MDIO_MMD_VEND1, 0, 9), },
1113 		NXP_C45_REG_FIELD(0x8351, MDIO_MMD_VEND1, 0, 14) },
1115 		NXP_C45_REG_FIELD(0xACA1, MDIO_MMD_VEND1, 0, 8), },
1117 		NXP_C45_REG_FIELD(0xACA0, MDIO_MMD_VEND1, 0, 16), },
1119 		NXP_C45_REG_FIELD(0xACA3, MDIO_MMD_VEND1, 0, 8), },
1121 		NXP_C45_REG_FIELD(0xACA2, MDIO_MMD_VEND1, 0, 16), },
1123 		NXP_C45_REG_FIELD(0xACA5, MDIO_MMD_VEND1, 0, 8), },
1125 		NXP_C45_REG_FIELD(0xACA4, MDIO_MMD_VEND1, 0, 16), },
1127 		NXP_C45_REG_FIELD(0xACA7, MDIO_MMD_VEND1, 0, 8), },
1129 		NXP_C45_REG_FIELD(0xACA6, MDIO_MMD_VEND1, 0, 16), },
1136 	return ARRAY_SIZE(common_hw_stats) + (phy_data ? phy_data->n_stats : 0);  in nxp_c45_get_sset_count()
1146 	for (i = 0; i < count; i++) {  in nxp_c45_get_strings()
1166 	for (i = 0; i < count; i++) {  in nxp_c45_get_stats()
1175 		if (ret < 0)  in nxp_c45_get_stats()
1196 	return 0;  in nxp_c45_config_enable()
1333 		return 0;  in nxp_c45_cable_test_get_status()
1409 	return 0;  in nxp_c45_check_delay()
1516 	return 0;  in nxp_c45_get_delays()
1526 	phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret);  in nxp_c45_set_phy_mode()
1598 	return 0;  in nxp_c45_set_phy_mode()
1607 	int ret = 0;  in nxp_c45_tja1120_errata()
1610 	if (ret < 0)  in nxp_c45_tja1120_errata()
1629 			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);  in nxp_c45_tja1120_errata()
1630 			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);  in nxp_c45_tja1120_errata()
1632 			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);  in nxp_c45_tja1120_errata()
1633 			phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);  in nxp_c45_tja1120_errata()
1636 		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);  in nxp_c45_tja1120_errata()
1638 		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a);  in nxp_c45_tja1120_errata()
1639 		phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1);  in nxp_c45_tja1120_errata()
1641 		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);  in nxp_c45_tja1120_errata()
1642 		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);  in nxp_c45_tja1120_errata()
1671 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1);  in nxp_c45_config_init()
1672 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2);  in nxp_c45_config_init()
1709 		return 0;  in nxp_c45_parse_dt()
1714 	return 0;  in nxp_c45_parse_dt()
1723 	int ret = 0;  in nxp_c45_probe()
1842 	.vend1_ptp_clk_period	= 0x1104,
1843 	.vend1_event_msg_filt	= 0x1148,
1845 		NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 3, 1),
1847 		NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 2, 1),
1849 		NXP_C45_REG_FIELD(0x1115, MDIO_MMD_VEND1, 0, 1),
1851 		NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 2, 1),
1853 		NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 0, 1),
1854 	.vend1_ltc_wr_nsec_0	= 0x1106,
1855 	.vend1_ltc_wr_nsec_1	= 0x1107,
1856 	.vend1_ltc_wr_sec_0	= 0x1108,
1857 	.vend1_ltc_wr_sec_1	= 0x1109,
1858 	.vend1_ltc_rd_nsec_0	= 0x110A,
1859 	.vend1_ltc_rd_nsec_1	= 0x110B,
1860 	.vend1_ltc_rd_sec_0	= 0x110C,
1861 	.vend1_ltc_rd_sec_1	= 0x110D,
1862 	.vend1_rate_adj_subns_0	= 0x110F,
1863 	.vend1_rate_adj_subns_1	= 0x1110,
1865 		NXP_C45_REG_FIELD(0x1131, MDIO_MMD_VEND1, 0, 1),
1867 		NXP_C45_REG_FIELD(0x1132, MDIO_MMD_VEND1, 0, 1),
1869 		NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 0, 8),
1871 		NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 8, 4),
1873 		NXP_C45_REG_FIELD(0x114F, MDIO_MMD_VEND1, 0, 16),
1875 		NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 14, 2),
1877 		NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 12, 3),
1879 		NXP_C45_REG_FIELD(0x1150, MDIO_MMD_VEND1, 0, 16),
1881 		NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 0, 14),
1882 	.vend1_ext_trg_data_0	= 0x1121,
1883 	.vend1_ext_trg_data_1	= 0x1122,
1884 	.vend1_ext_trg_data_2	= 0x1123,
1885 	.vend1_ext_trg_data_3	= 0x1124,
1886 	.vend1_ext_trg_ctrl	= 0x1126,
1887 	.cable_test		= 0x8330,
1889 		NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 13, 1),
1891 		NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 0, 3),
1992 	.vend1_ptp_clk_period	= 0x1020,
1993 	.vend1_event_msg_filt	= 0x9010,
1995 		NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 4, 1),
1997 		NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 5, 1),
1999 		NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 2, 1),
2001 		NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 1, 1),
2003 		NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 2, 1),
2004 	.vend1_ltc_wr_nsec_0	= 0x1040,
2005 	.vend1_ltc_wr_nsec_1	= 0x1041,
2006 	.vend1_ltc_wr_sec_0	= 0x1042,
2007 	.vend1_ltc_wr_sec_1	= 0x1043,
2008 	.vend1_ltc_rd_nsec_0	= 0x1048,
2009 	.vend1_ltc_rd_nsec_1	= 0x1049,
2010 	.vend1_ltc_rd_sec_0	= 0x104A,
2011 	.vend1_ltc_rd_sec_1	= 0x104B,
2012 	.vend1_rate_adj_subns_0	= 0x1030,
2013 	.vend1_rate_adj_subns_1	= 0x1031,
2015 		NXP_C45_REG_FIELD(0x900A, MDIO_MMD_VEND1, 1, 1),
2017 		NXP_C45_REG_FIELD(0x900C, MDIO_MMD_VEND1, 1, 1),
2019 		NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 8, 8),
2021 		NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 4, 4),
2023 		NXP_C45_REG_FIELD(0x9062, MDIO_MMD_VEND1, 0, 16),
2025 		NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 0, 2),
2027 		NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 2, 3),
2029 		NXP_C45_REG_FIELD(0x9063, MDIO_MMD_VEND1, 0, 16),
2031 		NXP_C45_REG_FIELD(0x9064, MDIO_MMD_VEND1, 0, 14),
2032 	.vend1_ext_trg_data_0	= 0x1071,
2033 	.vend1_ext_trg_data_1	= 0x1072,
2034 	.vend1_ext_trg_data_2	= 0x1073,
2035 	.vend1_ext_trg_data_3	= 0x1074,
2036 	.vend1_ext_trg_ctrl	= 0x1075,
2037 	.cable_test		= 0x8360,
2039 		NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 15, 1),
2041 		NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 0, 3),