Lines Matching refs:nxp_c45_macsec_write
290 static int nxp_c45_macsec_write(struct phy_device *phydev, u16 addr, u32 value) in nxp_c45_macsec_write() function
369 nxp_c45_macsec_write(phydev, MACSEC_EVER, reg); in nxp_c45_secy_irq_en()
474 nxp_c45_macsec_write(phydev, sa_regs->npn, npn.lower); in nxp_c45_sa_set_pn()
475 nxp_c45_macsec_write(phydev, sa_regs->xnpn, npn.upper); in nxp_c45_sa_set_pn()
484 nxp_c45_macsec_write(phydev, sa_regs->lnpn, lnpn.lower); in nxp_c45_sa_set_pn()
485 nxp_c45_macsec_write(phydev, sa_regs->lxnpn, lnpn.upper); in nxp_c45_sa_set_pn()
503 nxp_c45_macsec_write(phydev, reg, value); in nxp_c45_sa_set_key()
510 nxp_c45_macsec_write(phydev, reg, value); in nxp_c45_sa_set_key()
514 nxp_c45_macsec_write(phydev, sa_regs->ssci, value); in nxp_c45_sa_set_key()
517 nxp_c45_macsec_write(phydev, sa_regs->cs, MACSEC_SA_CS_A); in nxp_c45_sa_set_key()
523 nxp_c45_macsec_write(phydev, sa->regs->ipis, 0); in nxp_c45_rx_sa_clear_stats()
524 nxp_c45_macsec_write(phydev, sa->regs->ipnvs, 0); in nxp_c45_rx_sa_clear_stats()
525 nxp_c45_macsec_write(phydev, sa->regs->ipos, 0); in nxp_c45_rx_sa_clear_stats()
527 nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + sa->an * 4, 0); in nxp_c45_rx_sa_clear_stats()
528 nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + sa->an * 4, 0); in nxp_c45_rx_sa_clear_stats()
543 nxp_c45_macsec_write(phydev, sa->regs->opps, 0); in nxp_c45_tx_sa_clear_stats()
544 nxp_c45_macsec_write(phydev, sa->regs->opes, 0); in nxp_c45_tx_sa_clear_stats()
563 nxp_c45_macsec_write(phydev, sa_regs->cs, cfg); in nxp_c45_rx_sa_update()
586 nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg); in nxp_c45_tx_sa_update()
594 nxp_c45_macsec_write(phydev, sci_base_addr, lsci >> 32); in nxp_c45_set_sci()
595 nxp_c45_macsec_write(phydev, sci_base_addr + 4, lsci); in nxp_c45_set_sci()
607 nxp_c45_macsec_write(phydev, MACSEC_RXSCA, id); in nxp_c45_select_secy()
608 nxp_c45_macsec_write(phydev, MACSEC_RXSCKA, id); in nxp_c45_select_secy()
609 nxp_c45_macsec_write(phydev, MACSEC_TXSCA, id); in nxp_c45_select_secy()
610 nxp_c45_macsec_write(phydev, MACSEC_TXSCKA, id); in nxp_c45_select_secy()
680 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg); in nxp_c45_tx_sc_en_flt()
691 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_DA_SA(tx_flt_base), reg); in nxp_c45_tx_sc_set_flt()
695 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_SA(tx_flt_base), reg); in nxp_c45_tx_sc_set_flt()
699 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg); in nxp_c45_tx_sc_set_flt()
756 nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg); in nxp_c45_tx_sc_update()
768 nxp_c45_macsec_write(phydev, MACSEC_OPUS, 0); in nxp_c45_tx_sc_clear_stats()
769 nxp_c45_macsec_write(phydev, MACSEC_OPTLS, 0); in nxp_c45_tx_sc_clear_stats()
770 nxp_c45_macsec_write(phydev, MACSEC_OOP1HS, 0); in nxp_c45_tx_sc_clear_stats()
771 nxp_c45_macsec_write(phydev, MACSEC_OOP2HS, 0); in nxp_c45_tx_sc_clear_stats()
772 nxp_c45_macsec_write(phydev, MACSEC_OOE1HS, 0); in nxp_c45_tx_sc_clear_stats()
773 nxp_c45_macsec_write(phydev, MACSEC_OOE2HS, 0); in nxp_c45_tx_sc_clear_stats()
786 nxp_c45_macsec_write(phydev, MACSEC_CFG, reg); in nxp_c45_set_rx_sc0_impl()
810 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, reg); in nxp_c45_rx_sc_en()
831 nxp_c45_macsec_write(phydev, MACSEC_RPW, in nxp_c45_rx_sc_update()
857 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, cfg); in nxp_c45_rx_sc_update()
870 nxp_c45_macsec_write(phydev, MACSEC_INOD1HS, 0); in nxp_c45_rx_sc_clear_stats()
871 nxp_c45_macsec_write(phydev, MACSEC_INOD2HS, 0); in nxp_c45_rx_sc_clear_stats()
873 nxp_c45_macsec_write(phydev, MACSEC_INOV1HS, 0); in nxp_c45_rx_sc_clear_stats()
874 nxp_c45_macsec_write(phydev, MACSEC_INOV2HS, 0); in nxp_c45_rx_sc_clear_stats()
876 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPDS, 0); in nxp_c45_rx_sc_clear_stats()
877 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPLS, 0); in nxp_c45_rx_sc_clear_stats()
878 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPUS, 0); in nxp_c45_rx_sc_clear_stats()
881 nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + i * 4, 0); in nxp_c45_rx_sc_clear_stats()
882 nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + i * 4, 0); in nxp_c45_rx_sc_clear_stats()
891 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, 0); in nxp_c45_rx_sc_del()
892 nxp_c45_macsec_write(phydev, MACSEC_RPW, 0); in nxp_c45_rx_sc_del()
907 nxp_c45_macsec_write(phydev, MACSEC_INPBTS, 0); in nxp_c45_clear_global_stats()
908 nxp_c45_macsec_write(phydev, MACSEC_INPWTS, 0); in nxp_c45_clear_global_stats()
909 nxp_c45_macsec_write(phydev, MACSEC_IPSNFS, 0); in nxp_c45_clear_global_stats()
921 nxp_c45_macsec_write(phydev, MACSEC_CFG, reg); in nxp_c45_macsec_en()
1617 ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_CONFIG_EN | in nxp_c45_macsec_config_init()
1622 ret = nxp_c45_macsec_write(phydev, ADPTR_TX_TAG_CNTRL, in nxp_c45_macsec_config_init()
1627 ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_ADPTR_EN); in nxp_c45_macsec_config_init()
1631 ret = nxp_c45_macsec_write(phydev, MACSEC_TPNET, PN_WRAP_THRESHOLD); in nxp_c45_macsec_config_init()
1636 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0D2, ETH_P_PAE); in nxp_c45_macsec_config_init()
1640 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M1, MACSEC_OVP); in nxp_c45_macsec_config_init()
1644 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M2, ETYPE_MASK); in nxp_c45_macsec_config_init()
1648 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0R, MACSEC_UPFR_EN); in nxp_c45_macsec_config_init()
1725 nxp_c45_macsec_write(phydev, MACSEC_EVR, in nxp_c45_handle_macsec_interrupt()