Lines Matching +full:0 +full:x02d0
13 #define BIU_ADDR_EXE 0x8000
14 #define BIU_ADDR_READ 0x4000
15 #define BIU_ADDR_WRITE 0x0000
23 #define MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS 0x002d
24 #define MSCC_PHY_1588_VSC85XX_INT_STATUS 0x004d
25 #define VSC85XX_1588_INT_FIFO_ADD 0x0004
26 #define VSC85XX_1588_INT_FIFO_OVERFLOW 0x0001
28 #define MSCC_PHY_1588_INGR_VSC85XX_INT_MASK 0x002e
29 #define MSCC_PHY_1588_VSC85XX_INT_MASK 0x004e
34 #define MSCC_PHY_ANA_ETH1_NTX_PROT 0x0000
37 #define ANA_ETH1_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
38 #define ANA_ETH1_NTX_PROT_PTP_OAM 0x0005
39 #define ANA_ETH1_NTX_PROT_MPLS 0x0004
40 #define ANA_ETH1_NTX_PROT_IP_UDP_ACH_2 0x0003
41 #define ANA_ETH1_NTX_PROT_IP_UDP_ACH_1 0x0002
42 #define ANA_ETH1_NTX_PROT_ETH2 0x0001
44 #define MSCC_PHY_PTP_IFACE_CTRL 0x0000
45 #define PTP_IFACE_CTRL_CLK_ENA 0x0040
46 #define PTP_IFACE_CTRL_INGR_BYPASS 0x0008
47 #define PTP_IFACE_CTRL_EGR_BYPASS 0x0004
48 #define PTP_IFACE_CTRL_MII_PROT 0x0003
49 #define PTP_IFACE_CTRL_GMII_PROT 0x0002
50 #define PTP_IFACE_CTRL_XGMII_64_PROT 0x0000
52 #define MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID 0x0001
56 #define MSCC_PHY_PTP_ANALYZER_MODE 0x0001
57 #define PTP_ANA_SPLIT_ENCAP_FLOW 0x1000000
64 #define PTP_ANALYZER_MODE_INGR_ENA_MASK GENMASK(2, 0)
67 #define MSCC_PHY_ANA_ETH1_NXT_PROT_TAG 0x0002
68 #define ANA_ETH1_NXT_PROT_TAG_ENA 0x0001
70 #define MSCC_PHY_PTP_MODE_CTRL 0x0002
71 #define PTP_MODE_CTRL_MODE_MASK GENMASK(2, 0)
72 #define PTP_MODE_CTRL_PKT_MODE 0x0004
74 #define MSCC_PHY_ANA_ETH1_NXT_PROT_ETYPE_MATCH 0x0003
75 #define ANA_ETH1_NXT_PROT_ETYPE_MATCH_ENA 0x10000
76 #define ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK GENMASK(15, 0)
79 #define MSCC_PHY_PTP_VERSION_CODE 0x0003
80 #define PTP_IP_VERSION_MASK GENMASK(7, 0)
81 #define PTP_IP_VERSION_2_1 0x0021
83 #define MSCC_ANA_ETH1_FLOW_ENA(x) (0x0010 + ((x) << 4))
88 #define ETH1_FLOW_ENA 0x0001
93 #define ANA_ETH1_FLOW_MATCH_VLAN_TAG2 0x0200
94 #define ANA_ETH1_FLOW_MATCH_VLAN_VERIFY 0x0010
100 #define ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST 0x400000
101 #define ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR 0x100000
103 #define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST 0x020000
104 #define ANA_ETH1_FLOW_ADDR_MATCH2_SRC 0x010000
105 #define ANA_ETH1_FLOW_ADDR_MATCH2_DEST 0x000000
111 #define MSCC_PHY_PTP_LTC_CTRL 0x0010
115 #define PTP_LTC_CTRL_AUTO_ADJ_UPDATE 0x0010
116 #define PTP_LTC_CTRL_ADD_SUB_1NS_REQ 0x0008
117 #define PTP_LTC_CTRL_ADD_1NS 0x0004
118 #define PTP_LTC_CTRL_SAVE_ENA 0x0002
119 #define PTP_LTC_CTRL_LOAD_ENA 0x0001
121 #define MSCC_PHY_PTP_LTC_LOAD_SEC_MSB 0x0011
124 #define MSCC_PHY_PTP_LTC_LOAD_SEC_LSB 0x0012
125 #define PTP_LTC_LOAD_SEC_LSB(x) ((x) & GENMASK(31, 0))
127 #define MSCC_PHY_PTP_LTC_LOAD_NS 0x0013
128 #define PTP_LTC_LOAD_NS(x) ((x) & GENMASK(31, 0))
130 #define MSCC_PHY_PTP_LTC_SAVED_SEC_MSB 0x0014
131 #define MSCC_PHY_PTP_LTC_SAVED_SEC_LSB 0x0015
132 #define MSCC_PHY_PTP_LTC_SAVED_NS 0x0016
134 #define MSCC_PHY_PTP_LTC_SEQUENCE 0x0017
135 #define PTP_LTC_SEQUENCE_A_MASK GENMASK(3, 0)
138 #define MSCC_PHY_PTP_LTC_SEQ 0x0018
139 #define PTP_LTC_SEQ_ADD_SUB 0x80000
140 #define PTP_LTC_SEQ_ERR_MASK GENMASK(18, 0)
143 #define MSCC_PHY_PTP_LTC_AUTO_ADJ 0x001a
144 #define PTP_AUTO_ADJ_NS_ROLLOVER(x) ((x) & GENMASK(29, 0))
146 #define PTP_AUTO_ADJ_SUB_1NS 0x80000000
147 #define PTP_AUTO_ADJ_ADD_1NS 0x40000000
149 #define MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ 0x001b
150 #define PTP_LTC_1PPS_WIDTH_ADJ_MASK GENMASK(29, 0)
152 #define MSCC_PHY_PTP_TSTAMP_FIFO_SI 0x0020
153 #define PTP_TSTAMP_FIFO_SI_EN 0x0001
155 #define MSCC_PHY_PTP_INGR_PREDICTOR 0x0022
156 #define PTP_INGR_PREDICTOR_EN 0x0001
158 #define MSCC_PHY_PTP_EGR_PREDICTOR 0x0026
159 #define PTP_EGR_PREDICTOR_EN 0x0001
161 #define MSCC_PHY_PTP_INGR_TSP_CTRL 0x0035
162 #define PHY_PTP_INGR_TSP_CTRL_FRACT_NS 0x0004
163 #define PHY_PTP_INGR_TSP_CTRL_LOAD_DELAYS 0x0001
165 #define MSCC_PHY_PTP_INGR_LOCAL_LATENCY 0x0037
166 #define PTP_INGR_LOCAL_LATENCY_MASK GENMASK(22, 0)
169 #define MSCC_PHY_PTP_INGR_DELAY_FIFO 0x003a
170 #define PTP_INGR_DELAY_FIFO_DEPTH_MACSEC 0x0013
171 #define PTP_INGR_DELAY_FIFO_DEPTH_DEFAULT 0x000f
173 #define MSCC_PHY_PTP_INGR_TS_FIFO(x) (0x005c + (x))
174 #define PTP_INGR_TS_FIFO_EMPTY 0x80000000
176 #define MSCC_PHY_PTP_INGR_REWRITER_CTRL 0x0044
177 #define PTP_INGR_REWRITER_REDUCE_PREAMBLE 0x0010
178 #define PTP_INGR_REWRITER_FLAG_VAL 0x0008
179 #define PTP_INGR_REWRITER_FLAG_BIT_OFF_M GENMASK(2, 0)
182 #define MSCC_PHY_PTP_EGR_STALL_LATENCY 0x004f
184 #define MSCC_PHY_PTP_EGR_TSP_CTRL 0x0055
185 #define PHY_PTP_EGR_TSP_CTRL_FRACT_NS 0x0004
186 #define PHY_PTP_EGR_TSP_CTRL_LOAD_DELAYS 0x0001
188 #define MSCC_PHY_PTP_EGR_LOCAL_LATENCY 0x0057
189 #define PTP_EGR_LOCAL_LATENCY_MASK GENMASK(22, 0)
192 #define MSCC_PHY_PTP_EGR_DELAY_FIFO 0x005a
193 #define PTP_EGR_DELAY_FIFO_DEPTH_MACSEC 0x0013
194 #define PTP_EGR_DELAY_FIFO_DEPTH_DEFAULT 0x000f
196 #define MSCC_PHY_PTP_EGR_TS_FIFO_CTRL 0x005b
197 #define PTP_EGR_TS_FIFO_RESET 0x10000
202 #define PTP_EGR_TS_FIFO_SIG_BYTES_MASK GENMASK(4, 0)
205 #define MSCC_PHY_PTP_EGR_TS_FIFO(x) (0x005c + (x))
206 #define PTP_EGR_TS_FIFO_EMPTY 0x80000000
207 #define PTP_EGR_TS_FIFO_0_MASK GENMASK(15, 0)
209 #define MSCC_PHY_PTP_EGR_REWRITER_CTRL 0x0064
210 #define PTP_EGR_REWRITER_REDUCE_PREAMBLE 0x0010
211 #define PTP_EGR_REWRITER_FLAG_VAL 0x0008
212 #define PTP_EGR_REWRITER_FLAG_BIT_OFF_M GENMASK(2, 0)
215 #define MSCC_PHY_PTP_SERIAL_TOD_IFACE 0x006e
216 #define PTP_SERIAL_TOD_IFACE_LS_AUTO_CLR 0x0004
218 #define MSCC_PHY_PTP_LTC_OFFSET 0x0070
223 #define MSCC_PHY_PTP_ACCUR_CFG_STATUS 0x0074
224 #define PTP_ACCUR_PPS_OUT_CALIB_ERR 0x20000
225 #define PTP_ACCUR_PPS_OUT_CALIB_DONE 0x10000
226 #define PTP_ACCUR_PPS_IN_CALIB_ERR 0x4000
227 #define PTP_ACCUR_PPS_IN_CALIB_DONE 0x2000
228 #define PTP_ACCUR_EGR_SOF_CALIB_ERR 0x1000
229 #define PTP_ACCUR_EGR_SOF_CALIB_DONE 0x0800
230 #define PTP_ACCUR_INGR_SOF_CALIB_ERR 0x0400
231 #define PTP_ACCUR_INGR_SOF_CALIB_DONE 0x0200
232 #define PTP_ACCUR_LOAD_SAVE_CALIB_ERR 0x0100
233 #define PTP_ACCUR_LOAD_SAVE_CALIB_DONE 0x0080
234 #define PTP_ACCUR_CALIB_TRIGG 0x0040
235 #define PTP_ACCUR_PPS_OUT_BYPASS 0x0010
236 #define PTP_ACCUR_PPS_IN_BYPASS 0x0008
237 #define PTP_ACCUR_EGR_SOF_BYPASS 0x0004
238 #define PTP_ACCUR_INGR_SOF_BYPASS 0x0002
239 #define PTP_ACCUR_LOAD_SAVE_BYPASS 0x0001
241 #define MSCC_PHY_ANA_ETH2_NTX_PROT 0x0090
242 #define ANA_ETH2_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
243 #define ANA_ETH2_NTX_PROT_PTP_OAM 0x0005
244 #define ANA_ETH2_NTX_PROT_MPLS 0x0004
245 #define ANA_ETH2_NTX_PROT_IP_UDP_ACH_2 0x0003
246 #define ANA_ETH2_NTX_PROT_IP_UDP_ACH_1 0x0002
247 #define ANA_ETH2_NTX_PROT_ETH2 0x0001
249 #define MSCC_PHY_ANA_ETH2_NXT_PROT_ETYPE_MATCH 0x0003
250 #define ANA_ETH2_NXT_PROT_ETYPE_MATCH_ENA 0x10000
251 #define ANA_ETH2_NXT_PROT_ETYPE_MATCH_MASK GENMASK(15, 0)
254 #define MSCC_ANA_ETH2_FLOW_ENA(x) (0x00a0 + ((x) << 4))
260 #define MSCC_PHY_ANA_MPLS_COMP_NXT_COMP 0x0120
261 #define ANA_MPLS_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
262 #define ANA_MPLS_NTX_PROT_PTP_OAM 0x0005
263 #define ANA_MPLS_NTX_PROT_MPLS 0x0004
264 #define ANA_MPLS_NTX_PROT_IP_UDP_ACH_2 0x0003
265 #define ANA_MPLS_NTX_PROT_IP_UDP_ACH_1 0x0002
266 #define ANA_MPLS_NTX_PROT_ETH2 0x0001
268 #define MSCC_ANA_MPLS_FLOW_CTRL(x) (0x0130 + ((x) << 4))
274 #define MSCC_ANA_IP1_NXT_PROT_NXT_COMP 0x01b0
277 #define ANA_IP1_NXT_PROT_NXT_COMP_PTP_OAM 0x0005
278 #define ANA_IP1_NXT_PROT_NXT_COMP_IP_UDP_ACH2 0x0003
280 #define MSCC_ANA_IP1_NXT_PROT_IP1_MODE 0x01b1
281 #define ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV4 0x0c00
282 #define ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV6 0x0800
283 #define ANA_IP1_NXT_PROT_IPV6 0x0001
284 #define ANA_IP1_NXT_PROT_IPV4 0x0000
286 #define MSCC_ANA_IP1_NXT_PROT_IP_MATCH1 0x01b2
291 #define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH_MASK GENMASK(7, 0)
294 #define MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER 0x01b3
295 #define MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER 0x01b4
296 #define MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER 0x01b5
297 #define MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER 0x01b6
299 #define MSCC_ANA_IP1_NXT_PROT_OFFSET2 0x01b7
300 #define ANA_IP1_NXT_PROT_OFFSET2_MASK GENMASK(6, 0)
303 #define MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM 0x01b8
308 #define IP1_NXT_PROT_UDP_CHKSUM_UPDATE 0x0002
309 #define IP1_NXT_PROT_UDP_CHKSUM_CLEAR 0x0001
311 #define MSCC_ANA_IP1_FLOW_ENA(x) (0x01c0 + ((x) << 4))
313 #define IP1_FLOW_MATCH_DEST_SRC_ADDR 0x0200
314 #define IP1_FLOW_MATCH_DEST_ADDR 0x0100
315 #define IP1_FLOW_MATCH_SRC_ADDR 0x0000
320 #define IP1_FLOW_ENA 0x0001
322 #define MSCC_ANA_OAM_PTP_FLOW_ENA(x) (0x1e0 + ((x) << 4))
337 #define MSCC_ANA_IP2_NXT_PROT_NXT_COMP 0x0240
340 #define ANA_IP2_NXT_PROT_NXT_COMP_PTP_OAM 0x0005
341 #define ANA_IP2_NXT_PROT_NXT_COMP_IP_UDP_ACH2 0x0003
343 #define MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM 0x0248
349 #define MSCC_ANA_IP2_FLOW_ENA(x) (0x0250 + ((x) << 4))
355 #define MSCC_ANA_PTP_FLOW_ENA(x) (0x02d0 + ((x) << 4))
360 #define PTP_FLOW_ENA 0x0001
363 #define PTP_FLOW_MSG_TYPE_MASK 0x0F000000
364 #define PTP_FLOW_MSG_PDELAY_RESP 0x04000000
365 #define PTP_FLOW_MSG_PDELAY_REQ 0x02000000
366 #define PTP_FLOW_MSG_DELAY_REQ 0x01000000
367 #define PTP_FLOW_MSG_SYNC 0x00000000
374 #define PTP_FLOW_DOMAIN_RANGE_ENA 0x0001
377 #define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_UPDATE 0x10000000
380 #define PTP_FLOW_PTP_ACTION_PTP_CMD_MASK GENMASK(3, 0)
382 #define PTP_FLOW_PTP_ACTION_SUB_DELAY_ASYM 0x00200000
383 #define PTP_FLOW_PTP_ACTION_ADD_DELAY_ASYM 0x00100000
388 #define PTP_FLOW_PTP_ACTION_SAVE_LOCAL_TIME 0x00000010
393 #define PTP_FLOW_PTP_ACTION2_REWRITE_BYTES_MASK GENMASK(3, 0)
397 #define PTP_FLOW_PTP_0_FIELD_PTP_FRAME 0x8000
398 #define PTP_FLOW_PTP_0_FIELD_RSVRD_CHECK 0x4000
401 #define PTP_FLOW_PTP_0_FIELD_BYTES_MASK GENMASK(3, 0)
404 #define MSCC_ANA_PTP_IP_CHKSUM_SEL 0x0330
405 #define ANA_PTP_IP_CHKSUM_SEL_IP_COMP_2 0x0001
406 #define ANA_PTP_IP_CHKSUM_SEL_IP_COMP_1 0x0000
408 #define MSCC_PHY_ANA_FSB_CFG 0x331
409 #define ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK GENMASK(1, 0)
410 #define ANA_FSB_ADDR_FROM_IP2 0x0003
411 #define ANA_FSB_ADDR_FROM_IP1 0x0002
412 #define ANA_FSB_ADDR_FROM_ETH2 0x0001
413 #define ANA_FSB_ADDR_FROM_ETH1 0x0000
415 #define MSCC_PHY_ANA_FSB_REG(x) (0x332 + (x))
420 #define PPS_WIDTH_ADJ 0x1dcd6500
433 PTP_NOP = 0,