Lines Matching full:phydev
27 /* phydev->bus->mdio_lock should be locked when using this function */
28 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_ts_base_write() argument
30 struct vsc8531_private *priv = phydev->priv; in phy_ts_base_write()
32 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock)); in phy_ts_base_write()
33 return __mdiobus_write(phydev->mdio.bus, priv->ts_base_addr, regnum, in phy_ts_base_write()
37 /* phydev->bus->mdio_lock should be locked when using this function */
38 static int phy_ts_base_read(struct phy_device *phydev, u32 regnum) in phy_ts_base_read() argument
40 struct vsc8531_private *priv = phydev->priv; in phy_ts_base_read()
42 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock)); in phy_ts_base_read()
43 return __mdiobus_read(phydev->mdio.bus, priv->ts_base_addr, regnum); in phy_ts_base_read()
63 static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ts_read_csr() argument
66 struct vsc8531_private *priv = phydev->priv; in vsc85xx_ts_read_csr()
67 bool base_port = phydev->mdio.addr == priv->ts_base_addr; in vsc85xx_ts_read_csr()
84 phy_lock_mdio_bus(phydev); in vsc85xx_ts_read_csr()
86 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588); in vsc85xx_ts_read_csr()
88 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE | in vsc85xx_ts_read_csr()
93 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); in vsc85xx_ts_read_csr()
96 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB); in vsc85xx_ts_read_csr()
98 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB); in vsc85xx_ts_read_csr()
100 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc85xx_ts_read_csr()
102 phy_unlock_mdio_bus(phydev); in vsc85xx_ts_read_csr()
107 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ts_write_csr() argument
110 struct vsc8531_private *priv = phydev->priv; in vsc85xx_ts_write_csr()
111 bool base_port = phydev->mdio.addr == priv->ts_base_addr; in vsc85xx_ts_write_csr()
134 phy_lock_mdio_bus(phydev); in vsc85xx_ts_write_csr()
136 bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_ts_write_csr()
138 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588); in vsc85xx_ts_write_csr()
141 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_MSB, upper); in vsc85xx_ts_write_csr()
143 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_LSB, lower); in vsc85xx_ts_write_csr()
145 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE | in vsc85xx_ts_write_csr()
150 reg = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); in vsc85xx_ts_write_csr()
153 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc85xx_ts_write_csr()
156 phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass); in vsc85xx_ts_write_csr()
158 phy_unlock_mdio_bus(phydev); in vsc85xx_ts_write_csr()
167 static int vsc85xx_ts_fsb_init(struct phy_device *phydev) in vsc85xx_ts_fsb_init() argument
196 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(i), in vsc85xx_ts_fsb_init()
200 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(3), in vsc85xx_ts_fsb_init()
246 static void vsc85xx_ts_set_latencies(struct phy_device *phydev) in vsc85xx_ts_set_latencies() argument
252 if (!phydev->link) in vsc85xx_ts_set_latencies()
255 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY, in vsc85xx_ts_set_latencies()
256 STALL_EGR_LATENCY(phydev->speed)); in vsc85xx_ts_set_latencies()
258 switch (phydev->speed) { in vsc85xx_ts_set_latencies()
275 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
278 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_set_latencies()
281 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in vsc85xx_ts_set_latencies()
284 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
287 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in vsc85xx_ts_set_latencies()
289 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in vsc85xx_ts_set_latencies()
292 static int vsc85xx_ts_disable_flows(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_ts_disable_flows() argument
296 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
297 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, in vsc85xx_ts_disable_flows()
299 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
300 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM, in vsc85xx_ts_disable_flows()
302 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
303 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0); in vsc85xx_ts_disable_flows()
304 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0); in vsc85xx_ts_disable_flows()
307 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
309 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
311 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
313 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
315 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i), in vsc85xx_ts_disable_flows()
321 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0); in vsc85xx_ts_disable_flows()
322 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
324 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
326 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
328 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
330 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
332 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
334 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
336 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
338 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
345 static int vsc85xx_ts_eth_cmp1_sig(struct phy_device *phydev) in vsc85xx_ts_eth_cmp1_sig() argument
349 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_ts_eth_cmp1_sig()
352 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_ts_eth_cmp1_sig()
354 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG); in vsc85xx_ts_eth_cmp1_sig()
357 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val); in vsc85xx_ts_eth_cmp1_sig()
441 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, in vsc85xx_dequeue_skb()
451 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, in vsc85xx_dequeue_skb()
501 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR, in vsc85xx_get_tx_ts()
506 static int vsc85xx_ptp_cmp_init(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_ptp_cmp_init() argument
508 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_ptp_cmp_init()
509 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_ptp_cmp_init()
518 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), in vsc85xx_ptp_cmp_init()
522 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
525 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
528 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
532 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
540 static int vsc85xx_eth_cmp1_init(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_eth_cmp1_init() argument
542 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_eth_cmp1_init()
543 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_eth_cmp1_init()
546 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0); in vsc85xx_eth_cmp1_init()
547 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID, in vsc85xx_eth_cmp1_init()
550 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), in vsc85xx_eth_cmp1_init()
552 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), in vsc85xx_eth_cmp1_init()
554 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0); in vsc85xx_eth_cmp1_init()
555 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0); in vsc85xx_eth_cmp1_init()
556 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
558 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0); in vsc85xx_eth_cmp1_init()
559 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
562 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
566 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), in vsc85xx_eth_cmp1_init()
572 static int vsc85xx_ip_cmp1_init(struct phy_device *phydev, enum ts_blk blk) in vsc85xx_ip_cmp1_init() argument
574 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_ip_cmp1_init()
575 bool base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_ip_cmp1_init()
578 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER, in vsc85xx_ip_cmp1_init()
581 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER, in vsc85xx_ip_cmp1_init()
583 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER, in vsc85xx_ip_cmp1_init()
585 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0); in vsc85xx_ip_cmp1_init()
587 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip_cmp1_init()
590 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip_cmp1_init()
593 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0); in vsc85xx_ip_cmp1_init()
594 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0); in vsc85xx_ip_cmp1_init()
595 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0), in vsc85xx_ip_cmp1_init()
597 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0), in vsc85xx_ip_cmp1_init()
599 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0), in vsc85xx_ip_cmp1_init()
601 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0), in vsc85xx_ip_cmp1_init()
603 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0); in vsc85xx_ip_cmp1_init()
604 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0); in vsc85xx_ip_cmp1_init()
606 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0); in vsc85xx_ip_cmp1_init()
614 struct phy_device *phydev = ptp->phydev; in vsc85xx_adjfine() local
615 struct vsc8531_private *priv = phydev->priv; in vsc85xx_adjfine()
632 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_AUTO_ADJ, in vsc85xx_adjfine()
636 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in vsc85xx_adjfine()
638 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in vsc85xx_adjfine()
648 struct phy_device *phydev = ptp->phydev; in __vsc85xx_gettime() local
649 struct vsc8531_private *priv = phydev->priv; in __vsc85xx_gettime()
653 shared = phy_package_get_priv(phydev); in __vsc85xx_gettime()
655 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_gettime()
657 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_gettime()
665 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
670 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
674 ts->tv_nsec = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
686 struct phy_device *phydev = ptp->phydev; in vsc85xx_gettime() local
687 struct vsc8531_private *priv = phydev->priv; in vsc85xx_gettime()
700 struct phy_device *phydev = ptp->phydev; in __vsc85xx_settime() local
701 struct vsc8531_private *priv = phydev->priv; in __vsc85xx_settime()
705 shared = phy_package_get_priv(phydev); in __vsc85xx_settime()
707 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_MSB, in __vsc85xx_settime()
709 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_LSB, in __vsc85xx_settime()
711 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_NS, in __vsc85xx_settime()
714 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_settime()
716 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
725 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
737 struct phy_device *phydev = ptp->phydev; in vsc85xx_settime() local
738 struct vsc8531_private *priv = phydev->priv; in vsc85xx_settime()
750 struct phy_device *phydev = ptp->phydev; in vsc85xx_adjtime() local
751 struct vsc8531_private *priv = phydev->priv; in vsc85xx_adjtime()
776 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val); in vsc85xx_adjtime()
783 static int vsc85xx_eth1_next_comp(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_eth1_next_comp() argument
788 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_eth1_next_comp()
791 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_eth1_next_comp()
795 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_next_comp()
801 static int vsc85xx_ip1_next_comp(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ip1_next_comp() argument
804 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, in vsc85xx_ip1_next_comp()
811 static int vsc85xx_ts_ptp_action_flow(struct phy_device *phydev, enum ts_blk blk, u8 flow, enum ptp… in vsc85xx_ts_ptp_action_flow() argument
817 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_ptp_action_flow()
829 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow), in vsc85xx_ts_ptp_action_flow()
844 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_ptp_action_flow()
850 static int vsc85xx_ptp_conf(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ptp_conf() argument
862 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], in vsc85xx_ptp_conf()
866 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], in vsc85xx_ptp_conf()
869 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i], in vsc85xx_ptp_conf()
872 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_conf()
877 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), in vsc85xx_ptp_conf()
884 static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_eth1_conf() argument
887 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_eth1_conf()
896 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
898 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
904 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
906 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
910 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0)); in vsc85xx_eth1_conf()
914 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val); in vsc85xx_eth1_conf()
919 static int vsc85xx_ip1_conf(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ip1_conf() argument
924 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE, in vsc85xx_ip1_conf()
932 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1, in vsc85xx_ip1_conf()
936 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2, in vsc85xx_ip1_conf()
939 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ip1_conf()
953 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, in vsc85xx_ip1_conf()
956 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip1_conf()
961 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip1_conf()
966 static int vsc85xx_ts_engine_init(struct phy_device *phydev, bool one_step) in vsc85xx_ts_engine_init() argument
968 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_ts_engine_init()
969 bool ptp_l4, base = phydev->mdio.addr == vsc8531->ts_base_addr; in vsc85xx_ts_engine_init()
975 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_engine_init()
980 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in vsc85xx_ts_engine_init()
984 vsc85xx_eth1_next_comp(phydev, INGRESS, in vsc85xx_ts_engine_init()
986 vsc85xx_eth1_next_comp(phydev, EGRESS, in vsc85xx_ts_engine_init()
989 vsc85xx_eth1_next_comp(phydev, INGRESS, in vsc85xx_ts_engine_init()
992 vsc85xx_eth1_next_comp(phydev, EGRESS, in vsc85xx_ts_engine_init()
996 vsc85xx_ip1_next_comp(phydev, INGRESS, in vsc85xx_ts_engine_init()
998 vsc85xx_ip1_next_comp(phydev, EGRESS, in vsc85xx_ts_engine_init()
1002 vsc85xx_eth1_conf(phydev, INGRESS, in vsc85xx_ts_engine_init()
1004 vsc85xx_ip1_conf(phydev, INGRESS, in vsc85xx_ts_engine_init()
1006 vsc85xx_ptp_conf(phydev, INGRESS, one_step, in vsc85xx_ts_engine_init()
1009 vsc85xx_eth1_conf(phydev, EGRESS, in vsc85xx_ts_engine_init()
1011 vsc85xx_ip1_conf(phydev, EGRESS, in vsc85xx_ts_engine_init()
1013 vsc85xx_ptp_conf(phydev, EGRESS, one_step, in vsc85xx_ts_engine_init()
1024 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in vsc85xx_ts_engine_init()
1030 void vsc85xx_link_change_notify(struct phy_device *phydev) in vsc85xx_link_change_notify() argument
1032 struct vsc8531_private *priv = phydev->priv; in vsc85xx_link_change_notify()
1035 vsc85xx_ts_set_latencies(phydev); in vsc85xx_link_change_notify()
1039 static void vsc85xx_ts_reset_fifo(struct phy_device *phydev) in vsc85xx_ts_reset_fifo() argument
1043 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_reset_fifo()
1046 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in vsc85xx_ts_reset_fifo()
1050 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in vsc85xx_ts_reset_fifo()
1060 struct phy_device *phydev = vsc8531->ptp->phydev; in vsc85xx_hwtstamp() local
1097 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1100 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in vsc85xx_hwtstamp()
1102 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1105 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in vsc85xx_hwtstamp()
1109 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in vsc85xx_hwtstamp()
1115 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in vsc85xx_hwtstamp()
1118 vsc85xx_ts_reset_fifo(phydev); in vsc85xx_hwtstamp()
1120 vsc85xx_ts_engine_init(phydev, one_step); in vsc85xx_hwtstamp()
1123 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1126 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in vsc85xx_hwtstamp()
1128 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1131 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in vsc85xx_hwtstamp()
1221 struct phy_device *phydev = ptp->phydev; in vsc85xx_do_aux_work() local
1222 struct vsc8531_private *priv = phydev->priv; in vsc85xx_do_aux_work()
1265 static struct vsc8531_private *vsc8584_base_priv(struct phy_device *phydev) in vsc8584_base_priv() argument
1267 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_base_priv()
1269 if (vsc8531->ts_base_addr != phydev->mdio.addr) { in vsc8584_base_priv()
1272 dev = phydev->mdio.bus->mdio_map[vsc8531->ts_base_addr]; in vsc8584_base_priv()
1273 phydev = container_of(dev, struct phy_device, mdio); in vsc8584_base_priv()
1275 return phydev->priv; in vsc8584_base_priv()
1281 static bool vsc8584_is_1588_input_clk_configured(struct phy_device *phydev) in vsc8584_is_1588_input_clk_configured() argument
1283 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev); in vsc8584_is_1588_input_clk_configured()
1288 static void vsc8584_set_input_clk_configured(struct phy_device *phydev) in vsc8584_set_input_clk_configured() argument
1290 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev); in vsc8584_set_input_clk_configured()
1295 static int __vsc8584_init_ptp(struct phy_device *phydev) in __vsc8584_init_ptp() argument
1301 if (!vsc8584_is_1588_input_clk_configured(phydev)) { in __vsc8584_init_ptp()
1302 phy_lock_mdio_bus(phydev); in __vsc8584_init_ptp()
1307 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in __vsc8584_init_ptp()
1309 phy_ts_base_write(phydev, 29, 0x7ae0); in __vsc8584_init_ptp()
1310 phy_ts_base_write(phydev, 30, 0xb71c); in __vsc8584_init_ptp()
1311 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in __vsc8584_init_ptp()
1314 phy_unlock_mdio_bus(phydev); in __vsc8584_init_ptp()
1316 vsc8584_set_input_clk_configured(phydev); in __vsc8584_init_ptp()
1320 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1323 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in __vsc8584_init_ptp()
1325 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1328 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in __vsc8584_init_ptp()
1332 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc8584_init_ptp()
1335 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc8584_init_ptp()
1337 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE); in __vsc8584_init_ptp()
1340 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val); in __vsc8584_init_ptp()
1342 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ); in __vsc8584_init_ptp()
1347 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val); in __vsc8584_init_ptp()
1349 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ, in __vsc8584_init_ptp()
1352 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_DELAY_FIFO, in __vsc8584_init_ptp()
1357 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_DELAY_FIFO, in __vsc8584_init_ptp()
1363 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1373 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1376 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1379 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1382 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1390 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1393 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1396 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1399 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1402 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1406 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1409 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_TSTAMP_FIFO_SI, in __vsc8584_init_ptp()
1412 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1415 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1417 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1420 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1424 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1427 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1429 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1433 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1439 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1442 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in __vsc8584_init_ptp()
1445 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in __vsc8584_init_ptp()
1447 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in __vsc8584_init_ptp()
1449 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1452 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_SERIAL_TOD_IFACE, in __vsc8584_init_ptp()
1455 vsc85xx_ts_fsb_init(phydev); in __vsc8584_init_ptp()
1458 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1463 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in __vsc8584_init_ptp()
1466 vsc85xx_ts_reset_fifo(phydev); in __vsc8584_init_ptp()
1471 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1473 vsc85xx_ts_set_latencies(phydev); in __vsc8584_init_ptp()
1475 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_VERSION_CODE); in __vsc8584_init_ptp()
1477 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in __vsc8584_init_ptp()
1479 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1481 vsc85xx_ts_disable_flows(phydev, EGRESS); in __vsc8584_init_ptp()
1482 vsc85xx_ts_disable_flows(phydev, INGRESS); in __vsc8584_init_ptp()
1484 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1496 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in __vsc8584_init_ptp()
1504 vsc85xx_eth_cmp1_init(phydev, INGRESS); in __vsc8584_init_ptp()
1505 vsc85xx_ip_cmp1_init(phydev, INGRESS); in __vsc8584_init_ptp()
1506 vsc85xx_ptp_cmp_init(phydev, INGRESS); in __vsc8584_init_ptp()
1507 vsc85xx_eth_cmp1_init(phydev, EGRESS); in __vsc8584_init_ptp()
1508 vsc85xx_ip_cmp1_init(phydev, EGRESS); in __vsc8584_init_ptp()
1509 vsc85xx_ptp_cmp_init(phydev, EGRESS); in __vsc8584_init_ptp()
1511 vsc85xx_ts_eth_cmp1_sig(phydev); in __vsc8584_init_ptp()
1516 void vsc8584_config_ts_intr(struct phy_device *phydev) in vsc8584_config_ts_intr() argument
1518 struct vsc8531_private *priv = phydev->priv; in vsc8584_config_ts_intr()
1521 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_1588_VSC85XX_INT_MASK, in vsc8584_config_ts_intr()
1526 int vsc8584_ptp_init(struct phy_device *phydev) in vsc8584_ptp_init() argument
1528 switch (phydev->phy_id & phydev->drv->phy_id_mask) { in vsc8584_ptp_init()
1534 return __vsc8584_init_ptp(phydev); in vsc8584_ptp_init()
1540 void vsc8584_ptp_deinit(struct phy_device *phydev) in vsc8584_ptp_deinit() argument
1542 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_ptp_deinit()
1551 irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev) in vsc8584_handle_ts_interrupt() argument
1553 struct vsc8531_private *priv = phydev->priv; in vsc8584_handle_ts_interrupt()
1557 rc = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc8584_handle_ts_interrupt()
1560 vsc85xx_ts_write_csr(phydev, PROCESSOR, in vsc8584_handle_ts_interrupt()
1572 vsc85xx_ts_reset_fifo(phydev); in vsc8584_handle_ts_interrupt()
1579 int vsc8584_ptp_probe(struct phy_device *phydev) in vsc8584_ptp_probe() argument
1581 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_ptp_probe()
1583 vsc8531->ptp = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531->ptp), in vsc8584_ptp_probe()
1598 vsc8531->load_save = devm_gpiod_get_optional(&phydev->mdio.dev, "load-save", in vsc8584_ptp_probe()
1602 phydev_err(phydev, "Can't get load-save GPIO (%ld)\n", in vsc8584_ptp_probe()
1608 phydev->default_timestamp = true; in vsc8584_ptp_probe()
1610 vsc8531->ptp->phydev = phydev; in vsc8584_ptp_probe()
1616 phydev->mii_ts = &vsc8531->mii_ts; in vsc8584_ptp_probe()
1620 &phydev->mdio.dev); in vsc8584_ptp_probe()
1624 int vsc8584_ptp_probe_once(struct phy_device *phydev) in vsc8584_ptp_probe_once() argument
1626 struct vsc85xx_shared_private *shared = phy_package_get_priv(phydev); in vsc8584_ptp_probe_once()