Lines Matching defs:blk
63 static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,
71 switch (blk) {
107 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,
118 blk == PROCESSOR;
121 switch (blk) {
292 static int vsc85xx_ts_disable_flows(struct phy_device *phydev, enum ts_blk blk)
296 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0);
297 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,
299 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0);
300 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM,
302 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0);
303 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0);
304 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0);
307 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i),
309 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i),
311 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i),
313 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i),
315 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i),
321 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0);
322 vsc85xx_ts_write_csr(phydev, blk,
324 vsc85xx_ts_write_csr(phydev, blk,
326 vsc85xx_ts_write_csr(phydev, blk,
328 vsc85xx_ts_write_csr(phydev, blk,
330 vsc85xx_ts_write_csr(phydev, blk,
332 vsc85xx_ts_write_csr(phydev, blk,
334 vsc85xx_ts_write_csr(phydev, blk,
336 vsc85xx_ts_write_csr(phydev, blk,
338 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i),
506 static int vsc85xx_ptp_cmp_init(struct phy_device *phydev, enum ts_blk blk)
518 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),
522 val = vsc85xx_ts_read_csr(phydev, blk,
525 vsc85xx_ts_write_csr(phydev, blk,
528 vsc85xx_ts_write_csr(phydev, blk,
532 vsc85xx_ts_write_csr(phydev, blk,
540 static int vsc85xx_eth_cmp1_init(struct phy_device *phydev, enum ts_blk blk)
546 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0);
547 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID,
550 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0),
552 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),
554 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0);
555 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0);
556 vsc85xx_ts_write_csr(phydev, blk,
558 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0);
559 vsc85xx_ts_write_csr(phydev, blk,
562 val = vsc85xx_ts_read_csr(phydev, blk,
566 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),
572 static int vsc85xx_ip_cmp1_init(struct phy_device *phydev, enum ts_blk blk)
578 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER,
581 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER,
583 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER,
585 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0);
587 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));
590 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);
593 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0);
594 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0);
595 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0),
597 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0),
599 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0),
601 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0),
603 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0);
604 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0);
606 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0);
783 static int vsc85xx_eth1_next_comp(struct phy_device *phydev, enum ts_blk blk,
788 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT);
791 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val);
795 vsc85xx_ts_write_csr(phydev, blk,
801 static int vsc85xx_ip1_next_comp(struct phy_device *phydev, enum ts_blk blk,
804 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP,
811 static int vsc85xx_ts_ptp_action_flow(struct phy_device *phydev, enum ts_blk blk, u8 flow, enum ptp_cmd cmd)
817 vsc85xx_ts_write_csr(phydev, blk,
829 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow),
844 vsc85xx_ts_write_csr(phydev, blk,
850 static int vsc85xx_ptp_conf(struct phy_device *phydev, enum ts_blk blk,
861 if (blk == INGRESS)
862 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
866 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
869 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
872 val = vsc85xx_ts_read_csr(phydev, blk,
877 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),
884 static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk,
896 vsc85xx_ts_write_csr(phydev, blk,
898 vsc85xx_ts_write_csr(phydev, blk,
903 vsc85xx_ts_write_csr(phydev, blk,
905 vsc85xx_ts_write_csr(phydev, blk,
909 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0));
913 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val);
918 static int vsc85xx_ip1_conf(struct phy_device *phydev, enum ts_blk blk,
923 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE,
931 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1,
935 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2,
938 val = vsc85xx_ts_read_csr(phydev, blk,
952 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,
955 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));
960 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);