22 #define DP83867_DEVADDR		0x1f  macro
216 	val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);  in dp83867_set_wol()
230 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,  in dp83867_set_wol()
232 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,  in dp83867_set_wol()
234 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,  in dp83867_set_wol()
243 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,  in dp83867_set_wol()
245 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,  in dp83867_set_wol()
247 			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,  in dp83867_set_wol()
269 	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);  in dp83867_set_wol()
284 	value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);  in dp83867_get_wol()
296 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
301 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
306 		sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_get_wol()
501 		phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
504 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
517 		const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,  in dp83867_verify_rgmii_cfg()
700 	delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);  in dp83867_of_init()
778 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_init()
781 	bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);  in dp83867_config_init()
787 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
831 		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);  in dp83867_config_init()
846 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);  in dp83867_config_init()
858 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);  in dp83867_config_init()
867 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,  in dp83867_config_init()
873 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()
884 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
895 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
903 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);  in dp83867_config_init()
912 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);  in dp83867_config_init()
919 			phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_init()
946 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()
972 	err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,  in dp83867_phy_reset()