Lines Matching +full:tx +full:- +full:output +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
160 #define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
205 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
212 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
217 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
218 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
221 return -EINVAL; in dp83867_set_wol()
235 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
237 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
239 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
241 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
248 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
253 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
273 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
275 wol->wolopts = 0; in dp83867_get_wol()
280 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
283 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
286 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
291 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
292 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
296 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
297 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
301 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
302 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
304 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
308 wol->wolopts = 0; in dp83867_get_wol()
315 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
382 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
384 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
387 phydev->speed = SPEED_1000; in dp83867_read_status()
389 phydev->speed = SPEED_100; in dp83867_read_status()
391 phydev->speed = SPEED_10; in dp83867_read_status()
421 return -EINVAL; in dp83867_get_downshift()
434 return -E2BIG; in dp83867_set_downshift()
456 return -EINVAL; in dp83867_set_downshift()
470 switch (tuna->id) { in dp83867_get_tunable()
474 return -EOPNOTSUPP; in dp83867_get_tunable()
481 switch (tuna->id) { in dp83867_set_tunable()
485 return -EOPNOTSUPP; in dp83867_set_tunable()
491 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_port_mirroring()
493 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
505 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init_io_impedance()
506 struct device *dev = &phydev->mdio.dev; in dp83867_of_init_io_impedance()
507 struct device_node *of_node = dev->of_node; in dp83867_of_init_io_impedance()
515 if (ret != -ENOENT && ret != -EOPNOTSUPP) in dp83867_of_init_io_impedance()
520 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init_io_impedance()
521 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init_io_impedance()
522 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init_io_impedance()
523 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init_io_impedance()
525 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init_io_impedance()
541 return -ERANGE; in dp83867_of_init_io_impedance()
543 dp83867->io_impedance = val; in dp83867_of_init_io_impedance()
550 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
551 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
552 struct device_node *of_node = dev->of_node; in dp83867_of_init()
556 return -ENODEV; in dp83867_of_init()
559 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
560 &dp83867->clk_output_sel); in dp83867_of_init()
563 dp83867->set_clk_output = true; in dp83867_of_init()
567 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
568 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
569 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
570 dp83867->clk_output_sel); in dp83867_of_init()
571 return -EINVAL; in dp83867_of_init()
579 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
580 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
582 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
583 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
585 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_00_NS; in dp83867_of_init()
586 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
587 &dp83867->rx_id_delay); in dp83867_of_init()
588 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
590 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
591 dp83867->rx_id_delay); in dp83867_of_init()
592 return -EINVAL; in dp83867_of_init()
595 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_00_NS; in dp83867_of_init()
596 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
597 &dp83867->tx_id_delay); in dp83867_of_init()
598 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
600 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
601 dp83867->tx_id_delay); in dp83867_of_init()
602 return -EINVAL; in dp83867_of_init()
605 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
606 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
608 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
609 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
611 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
612 &dp83867->tx_fifo_depth); in dp83867_of_init()
614 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
615 &dp83867->tx_fifo_depth); in dp83867_of_init()
617 dp83867->tx_fifo_depth = in dp83867_of_init()
621 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
622 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
623 dp83867->tx_fifo_depth); in dp83867_of_init()
624 return -EINVAL; in dp83867_of_init()
627 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
628 &dp83867->rx_fifo_depth); in dp83867_of_init()
630 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
632 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
633 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
634 dp83867->rx_fifo_depth); in dp83867_of_init()
635 return -EINVAL; in dp83867_of_init()
643 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
646 /* For non-OF device, the RX and TX ID values are either strapped in dp83867_of_init()
647 * or take from default value. So, we init RX & TX ID values here in dp83867_of_init()
652 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; in dp83867_of_init()
653 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & in dp83867_of_init()
656 /* Per datasheet, IO impedance is default to 50-ohm, so we set the in dp83867_of_init()
660 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; in dp83867_of_init()
662 /* For non-OF device, the RX and TX FIFO depths are taken from in dp83867_of_init()
663 * default value. So, we init RX & TX FIFO depths here in dp83867_of_init()
666 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
667 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
677 phydev->interrupts = PHY_INTERRUPT_DISABLED; in dp83867_suspend()
688 phydev->interrupts = PHY_INTERRUPT_ENABLED; in dp83867_resume()
701 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
704 return -ENOMEM; in dp83867_probe()
706 phydev->priv = dp83867; in dp83867_probe()
713 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
722 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ in dp83867_config_init()
723 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
730 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
748 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
754 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
757 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
759 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
776 * Such N/A mode enabled by mistake can put PHY IC in some in dp83867_config_init()
777 * internal testing mode and disable RGMII transmission. in dp83867_config_init()
795 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
798 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
801 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
807 dp83867->rx_id_delay | in dp83867_config_init()
808 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); in dp83867_config_init()
812 if (dp83867->io_impedance >= 0) in dp83867_config_init()
815 dp83867->io_impedance); in dp83867_config_init()
817 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
818 /* For support SPEED_10 in SGMII mode in dp83867_config_init()
844 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
846 * switch on 6-wire mode. in dp83867_config_init()
848 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
855 * not strapped to mode 3 or 4 in HW. This is required for SGMII in dp83867_config_init()
858 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
864 /* Enable Interrupt output INT_OE in CFG3 register */ in dp83867_config_init()
871 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
874 /* Clock output selection if muxing property is set */ in dp83867_config_init()
875 if (dp83867->set_clk_output) { in dp83867_config_init()
878 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
882 val = dp83867->clk_output_sel << in dp83867_config_init()
931 * hence no new in-band message from PHY to MAC side SGMII. in dp83867_link_change_notify()
934 * SGMII wouldn`t receive new in-band message from TI PHY with in dp83867_link_change_notify()
936 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg in dp83867_link_change_notify()
939 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_link_change_notify()
955 return -EOPNOTSUPP; in dp83867_loopback()
968 return -EINVAL; in dp83867_led_brightness_set()
970 /* DRV_EN==1: output is DRV_VAL */ in dp83867_led_brightness_set()
985 return -EINVAL; in dp83867_led_mode()
1011 return -EOPNOTSUPP; in dp83867_led_mode()
1030 int mode, ret; in dp83867_led_hw_control_set() local
1032 mode = dp83867_led_mode(index, rules); in dp83867_led_hw_control_set()
1033 if (mode < 0) in dp83867_led_hw_control_set()
1034 return mode; in dp83867_led_hw_control_set()
1037 DP83867_LED_FN(index, mode)); in dp83867_led_hw_control_set()
1104 u32 mode; in dp83867_led_polarity_set() local
1106 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { in dp83867_led_polarity_set()
1107 switch (mode) { in dp83867_led_polarity_set()
1112 return -EINVAL; in dp83867_led_polarity_set()