Lines Matching +full:sgmii +full:- +full:ref +full:- +full:clock +full:- +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
205 struct net_device *ndev = phydev->attached_dev;
212 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
217 if (wol->wolopts & WAKE_MAGIC) {
218 mac = (const u8 *)ndev->dev_addr;
221 return -EINVAL;
235 if (wol->wolopts & WAKE_MAGICSECURE) {
237 (wol->sopass[1] << 8) | wol->sopass[0]);
239 (wol->sopass[3] << 8) | wol->sopass[2]);
241 (wol->sopass[5] << 8) | wol->sopass[4]);
248 if (wol->wolopts & WAKE_UCAST)
253 if (wol->wolopts & WAKE_BCAST)
273 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
275 wol->wolopts = 0;
280 wol->wolopts |= WAKE_UCAST;
283 wol->wolopts |= WAKE_BCAST;
286 wol->wolopts |= WAKE_MAGIC;
291 wol->sopass[0] = (sopass_val & 0xff);
292 wol->sopass[1] = (sopass_val >> 8);
296 wol->sopass[2] = (sopass_val & 0xff);
297 wol->sopass[3] = (sopass_val >> 8);
301 wol->sopass[4] = (sopass_val & 0xff);
302 wol->sopass[5] = (sopass_val >> 8);
304 wol->wolopts |= WAKE_MAGICSECURE;
308 wol->wolopts = 0;
315 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
382 phydev->duplex = DUPLEX_FULL;
384 phydev->duplex = DUPLEX_HALF;
387 phydev->speed = SPEED_1000;
389 phydev->speed = SPEED_100;
391 phydev->speed = SPEED_10;
398 int val, cnt, enable, count;
404 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
421 return -EINVAL;
424 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
434 return -E2BIG;
456 return -EINVAL;
470 switch (tuna->id) {
474 return -EOPNOTSUPP;
481 switch (tuna->id) {
485 return -EOPNOTSUPP;
491 struct dp83867_private *dp83867 = phydev->priv;
493 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
505 struct dp83867_private *dp83867 = phydev->priv;
506 struct device *dev = &phydev->mdio.dev;
507 struct device_node *of_node = dev->of_node;
515 if (ret != -ENOENT && ret != -EOPNOTSUPP)
520 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
521 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
522 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
523 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
525 dp83867->io_impedance = -1; /* leave at default */
541 return -ERANGE;
543 dp83867->io_impedance = val;
550 struct dp83867_private *dp83867 = phydev->priv;
551 struct device *dev = &phydev->mdio.dev;
552 struct device_node *of_node = dev->of_node;
556 return -ENODEV;
559 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
560 &dp83867->clk_output_sel);
563 dp83867->set_clk_output = true;
567 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
568 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
569 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
570 dp83867->clk_output_sel);
571 return -EINVAL;
579 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
580 "ti,dp83867-rxctrl-strap-quirk");
582 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
583 "ti,sgmii-ref-clock-output-enable");
585 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_00_NS;
586 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
587 &dp83867->rx_id_delay);
588 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
590 "ti,rx-internal-delay value of %u out of range\n",
591 dp83867->rx_id_delay);
592 return -EINVAL;
595 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_00_NS;
596 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
597 &dp83867->tx_id_delay);
598 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
600 "ti,tx-internal-delay value of %u out of range\n",
601 dp83867->tx_id_delay);
602 return -EINVAL;
605 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
606 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
608 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
609 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
611 ret = of_property_read_u32(of_node, "ti,fifo-depth",
612 &dp83867->tx_fifo_depth);
614 ret = of_property_read_u32(of_node, "tx-fifo-depth",
615 &dp83867->tx_fifo_depth);
617 dp83867->tx_fifo_depth =
621 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
622 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
623 dp83867->tx_fifo_depth);
624 return -EINVAL;
627 ret = of_property_read_u32(of_node, "rx-fifo-depth",
628 &dp83867->rx_fifo_depth);
630 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
632 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
633 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
634 dp83867->rx_fifo_depth);
635 return -EINVAL;
643 struct dp83867_private *dp83867 = phydev->priv;
646 /* For non-OF device, the RX and TX ID values are either strapped
652 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
653 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
656 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
660 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
662 /* For non-OF device, the RX and TX FIFO depths are taken from
666 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
667 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
677 phydev->interrupts = PHY_INTERRUPT_DISABLED;
686 /* Enable PHY Interrupts */
688 phydev->interrupts = PHY_INTERRUPT_ENABLED;
701 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
704 return -ENOMEM;
706 phydev->priv = dp83867;
713 struct dp83867_private *dp83867 = phydev->priv;
723 if (dp83867->rxctrl_strap_quirk)
729 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
730 * be set to 0x2. This may causes the PHY link to be unstable -
742 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
748 val |= (dp83867->tx_fifo_depth <<
751 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
753 val |= (dp83867->rx_fifo_depth <<
789 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
792 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
795 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
801 dp83867->rx_id_delay |
802 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
806 if (dp83867->io_impedance >= 0)
809 dp83867->io_impedance);
811 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
812 /* For support SPEED_10 in SGMII mode
825 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
838 /* SGMII type is set to 4-wire mode by default.
840 * switch on 6-wire mode.
842 if (dp83867->sgmii_ref_clk_en)
849 * not strapped to mode 3 or 4 in HW. This is required for SGMII
852 if (dp83867->rxctrl_strap_quirk)
858 /* Enable Interrupt output INT_OE in CFG3 register */
865 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
868 /* Clock output selection if muxing property is set */
869 if (dp83867->set_clk_output) {
872 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
876 val = dp83867->clk_output_sel <<
922 /* There is a limitation in DP83867 PHY device where SGMII AN is
924 * PHY TPI is down and up again, SGMII AN is not triggered and
925 * hence no new in-band message from PHY to MAC side SGMII.
927 * to MAC. At this condition, once MAC side SGMII is up, MAC side
928 * SGMII wouldn`t receive new in-band message from TI PHY with
930 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
933 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
946 static int dp83867_loopback(struct phy_device *phydev, bool enable, int speed)
948 if (enable && speed)
949 return -EOPNOTSUPP;
952 enable ? BMCR_LOOPBACK : 0);
962 return -EINVAL;
964 /* DRV_EN==1: output is DRV_VAL */
979 return -EINVAL;
1005 return -EOPNOTSUPP;
1106 return -EINVAL;