Lines Matching +full:ts +full:- +full:attached
1 // SPDX-License-Identifier: GPL-2.0+
145 /* list of the other attached phyters, not chosen */
165 static int chosen_phy = -1;
194 index = gpio_tab[CALIBRATE_GPIO] - 1;
198 index = gpio_tab[PEROUT_GPIO] - 1;
203 index = gpio_tab[i] - 1;
205 pd[index].chan = i - EXTTS0_GPIO;
222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
228 struct dp83640_private *dp83640 = phydev->priv;
231 if (dp83640->clock->page != page) {
233 dp83640->clock->page = page;
244 struct dp83640_private *dp83640 = phydev->priv;
246 if (dp83640->clock->page != page) {
248 dp83640->clock->page = page;
258 const struct timespec64 *ts, u16 cmd)
260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
276 sec = p->sec_lo;
277 sec |= p->sec_hi << 16;
279 rxts->ns = p->ns_lo;
280 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
281 rxts->ns += ((u64)sec) * 1000000000ULL;
282 rxts->seqid = p->seqid;
283 rxts->msgtype = (p->msgtype >> 12) & 0xf;
284 rxts->hash = p->msgtype & 0x0fff;
285 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
293 sec = p->sec_lo;
294 sec |= p->sec_hi << 16;
296 ns = p->ns_lo;
297 ns |= (p->ns_hi & 0x3fff) << 16;
307 struct dp83640_private *dp83640 = clock->chosen;
308 struct phy_device *phydev = dp83640->phydev;
313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
316 return -EINVAL;
331 mutex_lock(&clock->extreg_lock);
334 mutex_unlock(&clock->extreg_lock);
338 sec = clkreq->perout.start.sec;
339 nsec = clkreq->perout.start.nsec;
340 pwidth = clkreq->perout.period.sec * 1000000000UL;
341 pwidth += clkreq->perout.period.nsec;
344 mutex_lock(&clock->extreg_lock);
368 mutex_unlock(&clock->extreg_lock);
378 struct phy_device *phydev = clock->chosen->phydev;
385 scaled_ppm = -scaled_ppm;
397 mutex_lock(&clock->extreg_lock);
402 mutex_unlock(&clock->extreg_lock);
411 struct phy_device *phydev = clock->chosen->phydev;
412 struct timespec64 ts;
417 ts = ns_to_timespec64(delta);
419 mutex_lock(&clock->extreg_lock);
421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
423 mutex_unlock(&clock->extreg_lock);
429 struct timespec64 *ts)
433 struct phy_device *phydev = clock->chosen->phydev;
436 mutex_lock(&clock->extreg_lock);
445 mutex_unlock(&clock->extreg_lock);
447 ts->tv_nsec = val[0] | (val[1] << 16);
448 ts->tv_sec = val[2] | (val[3] << 16);
454 const struct timespec64 *ts)
458 struct phy_device *phydev = clock->chosen->phydev;
461 mutex_lock(&clock->extreg_lock);
463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
465 mutex_unlock(&clock->extreg_lock);
475 struct phy_device *phydev = clock->chosen->phydev;
479 switch (rq->type) {
482 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
486 return -EOPNOTSUPP;
489 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
490 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
491 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
492 return -EOPNOTSUPP;
494 index = rq->extts.index;
496 return -EINVAL;
500 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
503 return -EINVAL;
505 if (rq->extts.flags & PTP_FALLING_EDGE)
510 mutex_lock(&clock->extreg_lock);
512 mutex_unlock(&clock->extreg_lock);
517 if (rq->perout.flags)
518 return -EOPNOTSUPP;
519 if (rq->perout.index >= N_PER_OUT)
520 return -EINVAL;
521 return periodic_output(clock, rq, on, rq->perout.index);
527 return -EOPNOTSUPP;
536 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
537 !list_empty(&clock->phylist))
551 struct dp83640_private *dp83640 = phydev->priv;
552 struct dp83640_clock *clock = dp83640->clock;
560 mutex_lock(&clock->extreg_lock);
565 mutex_unlock(&clock->extreg_lock);
567 if (!phydev->attached_dev) {
569 "expected to find an attached netdevice\n");
574 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
577 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
587 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
595 return time_after(jiffies, rxts->tmo);
604 list_for_each_safe(this, next, &dp83640->rxts) {
607 list_del_init(&rxts->list);
608 list_add(&rxts->list, &dp83640->rxpool);
633 struct timespec64 ts;
635 struct phy_device *master = clock->chosen->phydev;
639 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
641 pr_err("PHY calibration pin not available - PHY is not calibrated.");
645 mutex_lock(&clock->extreg_lock);
650 list_for_each_entry(tmp, &clock->phylist, list) {
651 enable_broadcast(tmp->phydev, clock->page, 1);
652 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
653 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
654 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
656 enable_broadcast(master, clock->page, 1);
668 list_for_each_entry(tmp, &clock->phylist, list)
669 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
708 list_for_each_entry(tmp, &clock->phylist, list) {
709 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
710 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
711 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
712 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
713 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
714 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
715 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
716 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
717 diff = now - (s64) phy2txts(&event_ts);
718 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
721 ts = ns_to_timespec64(diff);
722 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
728 list_for_each_entry(tmp, &clock->phylist, list)
729 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
732 mutex_unlock(&clock->extreg_lock);
770 dp83640->edata.sec_hi = phy_txts->sec_hi;
773 dp83640->edata.sec_lo = phy_txts->sec_lo;
776 dp83640->edata.ns_hi = phy_txts->ns_hi;
779 dp83640->edata.ns_lo = phy_txts->ns_lo;
783 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
788 event.timestamp = phy2txts(&dp83640->edata);
791 event.timestamp -= 35;
796 ptp_clock_event(dp83640->clock->ptp_clock, &event);
812 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
820 if (rxts->msgtype != (msgtype & 0xf))
823 seqid = be16_to_cpu(hdr->sequence_id);
824 if (rxts->seqid != seqid)
828 (unsigned char *)&hdr->source_port_identity) >> 20;
829 if (rxts->hash != hash)
844 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
848 spin_lock_irqsave(&dp83640->rx_lock, flags);
852 if (list_empty(&dp83640->rxpool)) {
856 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
857 list_del_init(&rxts->list);
860 spin_lock(&dp83640->rx_queue.lock);
861 skb_queue_walk(&dp83640->rx_queue, skb) {
864 skb_info = (struct dp83640_skb_info *)skb->cb;
865 if (match(skb, skb_info->ptp_type, rxts)) {
866 __skb_unlink(skb, &dp83640->rx_queue);
869 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
870 list_add(&rxts->list, &dp83640->rxpool);
874 spin_unlock(&dp83640->rx_queue.lock);
877 list_add_tail(&rxts->list, &dp83640->rxts);
879 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
896 skb = skb_dequeue(&dp83640->tx_queue);
902 overflow = (phy_txts->ns_hi >> 14) & 0x3;
907 skb = skb_dequeue(&dp83640->tx_queue);
911 skb_info = (struct dp83640_skb_info *)skb->cb;
912 if (time_after(jiffies, skb_info->tmo)) {
932 ptr = skb->data + 2;
934 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
939 len -= sizeof(type);
975 if (!list_empty(&clock->phylist)) {
976 pr_warn("phy list non-empty while unloading\n");
979 list_del(&clock->list);
980 mutex_destroy(&clock->extreg_lock);
981 mutex_destroy(&clock->clock_lock);
982 put_device(&clock->bus->dev);
983 kfree(clock->caps.pin_config);
992 INIT_LIST_HEAD(&clock->list);
993 clock->bus = bus;
994 mutex_init(&clock->extreg_lock);
995 mutex_init(&clock->clock_lock);
996 INIT_LIST_HEAD(&clock->phylist);
997 clock->caps.owner = THIS_MODULE;
998 sprintf(clock->caps.name, "dp83640 timer");
999 clock->caps.max_adj = 1953124;
1000 clock->caps.n_alarm = 0;
1001 clock->caps.n_ext_ts = N_EXT_TS;
1002 clock->caps.n_per_out = N_PER_OUT;
1003 clock->caps.n_pins = DP83640_N_PINS;
1004 clock->caps.pps = 0;
1005 clock->caps.adjfine = ptp_dp83640_adjfine;
1006 clock->caps.adjtime = ptp_dp83640_adjtime;
1007 clock->caps.gettime64 = ptp_dp83640_gettime;
1008 clock->caps.settime64 = ptp_dp83640_settime;
1009 clock->caps.enable = ptp_dp83640_enable;
1010 clock->caps.verify = ptp_dp83640_verify;
1014 dp83640_gpio_defaults(clock->caps.pin_config);
1018 get_device(&bus->dev);
1024 if (chosen_phy == -1 && !clock->chosen)
1027 if (chosen_phy == phydev->mdio.addr)
1036 mutex_lock(&clock->clock_lock);
1053 if (tmp->bus == bus) {
1065 clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1068 if (!clock->caps.pin_config) {
1074 list_add_tail(&clock->list, &phyter_clocks);
1083 mutex_unlock(&clock->clock_lock);
1105 struct dp83640_private *dp83640 = phydev->priv;
1106 struct dp83640_clock *clock = dp83640->clock;
1108 if (clock->chosen && !list_empty(&clock->phylist))
1111 mutex_lock(&clock->extreg_lock);
1112 enable_broadcast(phydev, clock->page, 1);
1113 mutex_unlock(&clock->extreg_lock);
1118 mutex_lock(&clock->extreg_lock);
1120 mutex_unlock(&clock->extreg_lock);
1141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1218 if (cfg->tx_type < 0 || cfg->tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1219 return -ERANGE;
1221 dp83640->hwts_tx_en = cfg->tx_type;
1223 switch (cfg->rx_filter) {
1225 dp83640->hwts_rx_en = 0;
1226 dp83640->layer = 0;
1227 dp83640->version = 0;
1232 dp83640->hwts_rx_en = 1;
1233 dp83640->layer = PTP_CLASS_L4;
1234 dp83640->version = PTP_CLASS_V1;
1235 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1240 dp83640->hwts_rx_en = 1;
1241 dp83640->layer = PTP_CLASS_L4;
1242 dp83640->version = PTP_CLASS_V2;
1243 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1248 dp83640->hwts_rx_en = 1;
1249 dp83640->layer = PTP_CLASS_L2;
1250 dp83640->version = PTP_CLASS_V2;
1251 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1256 dp83640->hwts_rx_en = 1;
1257 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1258 dp83640->version = PTP_CLASS_V2;
1259 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1262 return -ERANGE;
1265 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1266 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1268 if (dp83640->layer & PTP_CLASS_L2) {
1272 if (dp83640->layer & PTP_CLASS_L4) {
1277 if (dp83640->hwts_tx_en)
1280 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1283 if (dp83640->hwts_rx_en)
1286 mutex_lock(&dp83640->clock->extreg_lock);
1288 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
1289 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1291 mutex_unlock(&dp83640->clock->extreg_lock);
1303 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1306 skb_info = (struct dp83640_skb_info *)skb->cb;
1307 if (!time_after(jiffies, skb_info->tmo)) {
1308 skb_queue_head(&dp83640->rx_queue, skb);
1315 if (!skb_queue_empty(&dp83640->rx_queue))
1316 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1324 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1336 if (!dp83640->hwts_rx_en)
1339 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1342 spin_lock_irqsave(&dp83640->rx_lock, flags);
1344 list_for_each_safe(this, next, &dp83640->rxts) {
1349 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1350 list_del_init(&rxts->list);
1351 list_add(&rxts->list, &dp83640->rxpool);
1355 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1358 skb_info->ptp_type = type;
1359 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1360 skb_queue_tail(&dp83640->rx_queue, skb);
1361 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1372 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1376 switch (dp83640->hwts_tx_en) {
1385 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1386 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1387 skb_queue_tail(&dp83640->tx_queue, skb);
1403 info->so_timestamping =
1407 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1408 info->tx_types =
1412 info->rx_filters =
1425 int err = -ENOMEM, i;
1427 if (phydev->mdio.addr == BROADCAST_ADDR)
1430 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1438 dp83640->phydev = phydev;
1439 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp;
1440 dp83640->mii_ts.txtstamp = dp83640_txtstamp;
1441 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp;
1442 dp83640->mii_ts.ts_info = dp83640_ts_info;
1444 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1445 INIT_LIST_HEAD(&dp83640->rxts);
1446 INIT_LIST_HEAD(&dp83640->rxpool);
1448 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1451 phydev->default_timestamp = true;
1452 phydev->mii_ts = &dp83640->mii_ts;
1453 phydev->priv = dp83640;
1455 spin_lock_init(&dp83640->rx_lock);
1456 skb_queue_head_init(&dp83640->rx_queue);
1457 skb_queue_head_init(&dp83640->tx_queue);
1459 dp83640->clock = clock;
1462 clock->chosen = dp83640;
1463 clock->ptp_clock = ptp_clock_register(&clock->caps,
1464 &phydev->mdio.dev);
1465 if (IS_ERR(clock->ptp_clock)) {
1466 err = PTR_ERR(clock->ptp_clock);
1470 list_add_tail(&dp83640->list, &clock->phylist);
1476 clock->chosen = NULL;
1488 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1490 if (phydev->mdio.addr == BROADCAST_ADDR)
1493 phydev->mii_ts = NULL;
1496 cancel_delayed_work_sync(&dp83640->ts_work);
1498 skb_queue_purge(&dp83640->rx_queue);
1499 skb_queue_purge(&dp83640->tx_queue);
1501 clock = dp83640_clock_get(dp83640->clock);
1503 if (dp83640 == clock->chosen) {
1504 ptp_clock_unregister(clock->ptp_clock);
1505 clock->chosen = NULL;
1507 list_for_each_safe(this, next, &clock->phylist) {
1510 list_del_init(&tmp->list);