Lines Matching defs:clock
107 struct dp83640_clock *clock;
133 /* we create one clock instance per MII bus */
147 /* reference to our PTP hardware clock */
174 "The address of the PHY to use for the ancillary clock features");
231 if (dp83640->clock->page != page) {
233 dp83640->clock->page = page;
246 if (dp83640->clock->page != page) {
248 dp83640->clock->page = page;
303 static int periodic_output(struct dp83640_clock *clock,
307 struct dp83640_private *dp83640 = clock->chosen;
313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
331 mutex_lock(&clock->extreg_lock);
334 mutex_unlock(&clock->extreg_lock);
344 mutex_lock(&clock->extreg_lock);
368 mutex_unlock(&clock->extreg_lock);
372 /* ptp clock methods */
376 struct dp83640_clock *clock =
378 struct phy_device *phydev = clock->chosen->phydev;
397 mutex_lock(&clock->extreg_lock);
402 mutex_unlock(&clock->extreg_lock);
409 struct dp83640_clock *clock =
411 struct phy_device *phydev = clock->chosen->phydev;
419 mutex_lock(&clock->extreg_lock);
423 mutex_unlock(&clock->extreg_lock);
431 struct dp83640_clock *clock =
433 struct phy_device *phydev = clock->chosen->phydev;
436 mutex_lock(&clock->extreg_lock);
445 mutex_unlock(&clock->extreg_lock);
456 struct dp83640_clock *clock =
458 struct phy_device *phydev = clock->chosen->phydev;
461 mutex_lock(&clock->extreg_lock);
465 mutex_unlock(&clock->extreg_lock);
473 struct dp83640_clock *clock =
475 struct phy_device *phydev = clock->chosen->phydev;
500 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
510 mutex_lock(&clock->extreg_lock);
512 mutex_unlock(&clock->extreg_lock);
521 return periodic_output(clock, rq, on, rq->perout.index);
533 struct dp83640_clock *clock =
536 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
537 !list_empty(&clock->phylist))
552 struct dp83640_clock *clock = dp83640->clock;
560 mutex_lock(&clock->extreg_lock);
565 mutex_unlock(&clock->extreg_lock);
613 /* synchronize the phyters so they act as one clock */
629 static void recalibrate(struct dp83640_clock *clock)
635 struct phy_device *master = clock->chosen->phydev;
639 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
645 mutex_lock(&clock->extreg_lock);
648 * enable broadcast, disable status frames, enable ptp clock
650 list_for_each_entry(tmp, &clock->phylist, list) {
651 enable_broadcast(tmp->phydev, clock->page, 1);
656 enable_broadcast(master, clock->page, 1);
668 list_for_each_entry(tmp, &clock->phylist, list)
708 list_for_each_entry(tmp, &clock->phylist, list) {
728 list_for_each_entry(tmp, &clock->phylist, list)
732 mutex_unlock(&clock->extreg_lock);
796 ptp_clock_event(dp83640->clock->ptp_clock, &event);
968 struct dp83640_clock *clock;
974 clock = list_entry(this, struct dp83640_clock, list);
975 if (!list_empty(&clock->phylist)) {
979 list_del(&clock->list);
980 mutex_destroy(&clock->extreg_lock);
981 mutex_destroy(&clock->clock_lock);
982 put_device(&clock->bus->dev);
983 kfree(clock->caps.pin_config);
984 kfree(clock);
990 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
992 INIT_LIST_HEAD(&clock->list);
993 clock->bus = bus;
994 mutex_init(&clock->extreg_lock);
995 mutex_init(&clock->clock_lock);
996 INIT_LIST_HEAD(&clock->phylist);
997 clock->caps.owner = THIS_MODULE;
998 sprintf(clock->caps.name, "dp83640 timer");
999 clock->caps.max_adj = 1953124;
1000 clock->caps.n_alarm = 0;
1001 clock->caps.n_ext_ts = N_EXT_TS;
1002 clock->caps.n_per_out = N_PER_OUT;
1003 clock->caps.n_pins = DP83640_N_PINS;
1004 clock->caps.pps = 0;
1005 clock->caps.adjfine = ptp_dp83640_adjfine;
1006 clock->caps.adjtime = ptp_dp83640_adjtime;
1007 clock->caps.gettime64 = ptp_dp83640_gettime;
1008 clock->caps.settime64 = ptp_dp83640_settime;
1009 clock->caps.enable = ptp_dp83640_enable;
1010 clock->caps.verify = ptp_dp83640_verify;
1014 dp83640_gpio_defaults(clock->caps.pin_config);
1021 static int choose_this_phy(struct dp83640_clock *clock,
1024 if (chosen_phy == -1 && !clock->chosen)
1033 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1035 if (clock)
1036 mutex_lock(&clock->clock_lock);
1037 return clock;
1041 * Look up and lock a clock by bus instance.
1042 * If there is no clock for this bus, then create it first.
1046 struct dp83640_clock *clock = NULL, *tmp;
1054 clock = tmp;
1058 if (clock)
1061 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1062 if (!clock)
1065 clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1068 if (!clock->caps.pin_config) {
1069 kfree(clock);
1070 clock = NULL;
1073 dp83640_clock_init(clock, bus);
1074 list_add_tail(&clock->list, &phyter_clocks);
1078 return dp83640_clock_get(clock);
1081 static void dp83640_clock_put(struct dp83640_clock *clock)
1083 mutex_unlock(&clock->clock_lock);
1106 struct dp83640_clock *clock = dp83640->clock;
1108 if (clock->chosen && !list_empty(&clock->phylist))
1109 recalibrate(clock);
1111 mutex_lock(&clock->extreg_lock);
1112 enable_broadcast(phydev, clock->page, 1);
1113 mutex_unlock(&clock->extreg_lock);
1118 mutex_lock(&clock->extreg_lock);
1120 mutex_unlock(&clock->extreg_lock);
1286 mutex_lock(&dp83640->clock->extreg_lock);
1291 mutex_unlock(&dp83640->clock->extreg_lock);
1407 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1423 struct dp83640_clock *clock;
1430 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1431 if (!clock)
1459 dp83640->clock = clock;
1461 if (choose_this_phy(clock, phydev)) {
1462 clock->chosen = dp83640;
1463 clock->ptp_clock = ptp_clock_register(&clock->caps,
1465 if (IS_ERR(clock->ptp_clock)) {
1466 err = PTR_ERR(clock->ptp_clock);
1470 list_add_tail(&dp83640->list, &clock->phylist);
1472 dp83640_clock_put(clock);
1476 clock->chosen = NULL;
1479 dp83640_clock_put(clock);
1486 struct dp83640_clock *clock;
1501 clock = dp83640_clock_get(dp83640->clock);
1503 if (dp83640 == clock->chosen) {
1504 ptp_clock_unregister(clock->ptp_clock);
1505 clock->chosen = NULL;
1507 list_for_each_safe(this, next, &clock->phylist) {
1516 dp83640_clock_put(clock);