Lines Matching +full:100 +full:bt

64 	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */  in bcm7xxx_28nm_d0_afe_config_init()
70 	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */  in bcm7xxx_28nm_d0_afe_config_init()
73 	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal  in bcm7xxx_28nm_d0_afe_config_init()
95 	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */  in bcm7xxx_28nm_e0_plus_afe_config_init()
101 	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal  in bcm7xxx_28nm_e0_plus_afe_config_init()
132 	/* Change 100Tx EEE bandwidth */  in bcm7xxx_28nm_a0_patch_afe_config_init()
475 	udelay(100);  in bcm7xxx_16nm_ephy_afe_config()
481 	udelay(100);  in bcm7xxx_16nm_ephy_afe_config()
483 	/* Adjust 10BT amplitude additional +7% and 100BT +2% */  in bcm7xxx_16nm_ephy_afe_config()
505 	/* AFE_BIAS_CONFIG_0 10BT bias code (Bias: E4) */  in bcm7xxx_16nm_ephy_afe_config()
511 	/* 100BT stair case, high BW, 1G stair case, alternate encode */  in bcm7xxx_16nm_ephy_afe_config()
513 	/* 1000BT DAC transition method per Erol, bits[32], DAC Shuffle  in bcm7xxx_16nm_ephy_afe_config()
514 	 * sequence 1 + 10BT imp adjust bits  in bcm7xxx_16nm_ephy_afe_config()