1 // SPDX-License-Identifier: GPL-2.0
2 /* Airoha AN7583 MDIO interface driver
51 	return regmap_read_poll_timeout(priv->regmap, priv->base_addr, busy,  in airoha_mdio_wait_busy()
64 	 *  - read at 0x1f report at 0x2 0x7500  in airoha_mdio_reset()
65 	 *  - read at 0x0 report 0x7500 on every address  in airoha_mdio_reset()
67 	 * To workaround this, we reset the Mdio BUS at every read  in airoha_mdio_reset()
70 	reset_control_assert(priv->reset);  in airoha_mdio_reset()
71 	reset_control_deassert(priv->reset);  in airoha_mdio_reset()
76 	struct airoha_mdio_data *priv = bus->priv;  in airoha_mdio_read()
87 	ret = regmap_write(priv->regmap, priv->base_addr, val);  in airoha_mdio_read()
95 	ret = regmap_read(priv->regmap, priv->base_addr, &val);  in airoha_mdio_read()
105 	struct airoha_mdio_data *priv = bus->priv;  in airoha_mdio_write()
115 	ret = regmap_write(priv->regmap, priv->base_addr, val);  in airoha_mdio_write()
127 	struct airoha_mdio_data *priv = bus->priv;  in airoha_mdio_cl45_read()
139 	ret = regmap_write(priv->regmap, priv->base_addr, val);  in airoha_mdio_cl45_read()
152 	ret = regmap_write(priv->regmap, priv->base_addr, val);  in airoha_mdio_cl45_read()
160 	ret = regmap_read(priv->regmap, priv->base_addr, &val);  in airoha_mdio_cl45_read()
170 	struct airoha_mdio_data *priv = bus->priv;  in airoha_mdio_cl45_write()
180 	ret = regmap_write(priv->regmap, priv->base_addr, val);  in airoha_mdio_cl45_write()
194 	ret = regmap_write(priv->regmap, priv->base_addr, val);  in airoha_mdio_cl45_write()
205 	struct device *dev = &pdev->dev;  in airoha_mdio_probe()
211 	ret = of_property_read_u32(dev->of_node, "reg", &addr);  in airoha_mdio_probe()
217 		return -ENOMEM;  in airoha_mdio_probe()
219 	priv = bus->priv;  in airoha_mdio_probe()
220 	priv->base_addr = addr;  in airoha_mdio_probe()
221 	priv->regmap = device_node_to_regmap(dev->parent->of_node);  in airoha_mdio_probe()
223 	priv->clk = devm_clk_get_enabled(dev, NULL);  in airoha_mdio_probe()
224 	if (IS_ERR(priv->clk))  in airoha_mdio_probe()
225 		return PTR_ERR(priv->clk);  in airoha_mdio_probe()
227 	priv->reset = devm_reset_control_get_exclusive(dev, NULL);  in airoha_mdio_probe()
228 	if (IS_ERR(priv->reset))  in airoha_mdio_probe()
229 		return PTR_ERR(priv->reset);  in airoha_mdio_probe()
231 	reset_control_deassert(priv->reset);  in airoha_mdio_probe()
233 	bus->name = "airoha_mdio_bus";  in airoha_mdio_probe()
234 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));  in airoha_mdio_probe()
235 	bus->parent = dev;  in airoha_mdio_probe()
236 	bus->read = airoha_mdio_read;  in airoha_mdio_probe()
237 	bus->write = airoha_mdio_write;  in airoha_mdio_probe()
238 	bus->read_c45 = airoha_mdio_cl45_read;  in airoha_mdio_probe()
239 	bus->write_c45 = airoha_mdio_cl45_write;  in airoha_mdio_probe()
242 	if (of_property_read_u32(dev->of_node, "clock-frequency", &freq))  in airoha_mdio_probe()
245 	ret = clk_set_rate(priv->clk, freq);  in airoha_mdio_probe()
249 	ret = devm_of_mdiobus_register(dev, bus, dev->of_node);  in airoha_mdio_probe()
251 		reset_control_assert(priv->reset);  in airoha_mdio_probe()
259 	{ .compatible = "airoha,an7583-mdio" },
267 		.name = "airoha-mdio",
274 MODULE_DESCRIPTION("Airoha AN7583 MDIO interface driver");