Lines Matching +full:phy +full:- +full:is +full:- +full:integrated

1 # SPDX-License-Identifier: GPL-2.0-only
17 	  FWNODE MDIO bus (Ethernet PHY) accessors
23 	  OpenFirmware MDIO bus (Ethernet PHY) accessors
28 	  ACPI MDIO bus (Ethernet PHY) accessors
46 	tristate "APM X-Gene SoC MDIO bus controller"
50 	  APM X-Gene SoC's.
58 	  controllers found in the ASPEED AST2600 SoC. This is a driver for the
59 	  third revision of the ASPEED MDIO register interface - the first two
63 	  AST2500 SoCs, so say N if AST2600 support is not required.
96 	tristate "GPIO lib-based bitbanged MDIO buses"
100 	  Supports GPIO lib-based MDIO busses.
103 	  will be called mdio-gpio.
120 	  This is library mode.
134 	  switches of the Microsemi SoCs; it is recommended to switch on
151 	  buses. It is required by the Octeon and ThunderX ethernet device
160 	  IPQ40xx, IPQ60xx, IPQ807x and IPQ50xx series Soc-s.
175 	  RTL9300 family of Ethernet switches with integrated SoC.
182 	  layout. It's regmap-based so that it can be used on integrated,
183 	  memory-mapped PHYs, SPI PHYs and so on. A new virtual MDIO bus is
206 	  to a parent bus.  Switching between child busses is done by
261 	  selection is under the control of GPIO lines.
270 	  that is controlled via the kernel multiplexer subsystem. The
272 	  a parent bus.  Child bus selection is under the control of
276 	tristate "MMIO device-controlled MDIO bus multiplexers"
281 	  are controlled via a simple memory-mapped device, like an FPGA.
283 	  parent bus.  Child bus selection is under the control of one of