Lines Matching +full:control +full:- +full:parent

1 # SPDX-License-Identifier: GPL-2.0-only
46 	tristate "APM X-Gene SoC MDIO bus controller"
50 	  APM X-Gene SoC's.
59 	  third revision of the ASPEED MDIO register interface - the first two
96 	tristate "GPIO lib-based bitbanged MDIO buses"
100 	  Supports GPIO lib-based MDIO busses.
103 	  will be called mdio-gpio.
160 	  IPQ40xx, IPQ60xx, IPQ807x and IPQ50xx series Soc-s.
182 	  layout. It's regmap-based so that it can be used on integrated,
183 	  memory-mapped PHYs, SPI PHYs and so on. A new virtual MDIO bus is
206 	  to a parent bus.  Switching between child busses is done by
218 	  or the internal MDIO bus to the parent bus.
229 	  or the internal MDIO bus to the parent bus.
239 	  child MDIO bus to a parent bus. Buses could be internal as well as
250 	  child MDIO bus to a parent bus. Buses could be internal as well as
260 	  several child MDIO busses to a parent bus.  Child bus
261 	  selection is under the control of GPIO lines.
272 	  a parent bus.  Child bus selection is under the control of
276 	tristate "MMIO device-controlled MDIO bus multiplexers"
281 	  are controlled via a simple memory-mapped device, like an FPGA.
283 	  parent bus.  Child bus selection is under the control of one of