Lines Matching full:ipa
13 struct ipa;
16 * DOC: IPA Registers
18 * IPA registers are located within the "ipa-reg" address space defined by
22 * All IPA registers are 32 bits wide.
25 * instances of something. For example, each IPA endpoint has an set of
33 * Each version of IPA implements an array of ipa_reg structures indexed
36 * of IPA define all registers. The offset for a register is returned by
53 /* enum ipa_reg_id - IPA register IDs */
61 FILT_ROUT_HASH_EN, /* IPA v4.2 */
62 FILT_ROUT_HASH_FLUSH, /* Not IPA v4.2 nor IPA v5.0+ */
63 FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */
65 IPA_BCR, /* Not IPA v4.5+ */
68 COUNTER_CFG, /* Not IPA v4.5+ */
69 IPA_TX_CFG, /* IPA v3.5+ */
70 FLAVOR_0, /* IPA v3.5+ */
71 IDLE_INDICATION_CFG, /* IPA v3.5+ */
72 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */
73 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */
74 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */
77 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
78 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
81 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
82 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
83 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */
97 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */
98 ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */
99 ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */
106 IRQ_SUSPEND_EN, /* IPA v3.1+ */
107 IRQ_SUSPEND_CLR, /* IPA v3.1+ */
113 COMP_CFG_ENABLE, /* Not IPA v4.0+ */
114 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */
118 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */
119 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */
120 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */
121 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
122 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
123 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
124 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
125 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
126 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
127 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */
128 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */
129 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */
130 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */
131 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */
132 GENQMB_AOOOWR, /* IPA v4.9+ */
133 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */
134 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */
135 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */
136 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */
137 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */
159 CLKON_DCMP, /* IPA v4.5+ */
160 NTF_TX_CMDQS, /* IPA v3.5+ */
161 CLKON_TX_0, /* IPA v3.5+ */
162 CLKON_TX_1, /* IPA v3.5+ */
163 CLKON_FNR, /* IPA v3.5.1+ */
164 QSB2AXI_CMDQ_L, /* IPA v4.0+ */
165 AGGR_WRAPPER, /* IPA v4.0+ */
166 RAM_SLAVEWAY, /* IPA v4.0+ */
167 CLKON_QMB, /* IPA v4.0+ */
168 WEIGHT_ARB, /* IPA v4.0+ */
169 GSI_IF, /* IPA v4.0+ */
170 CLKON_GLOBAL, /* IPA v4.0+ */
171 GLOBAL_2X_CLK, /* IPA v4.0+ */
172 DPL_FIFO, /* IPA v4.5+ */
173 DRBIP, /* IPA v4.7+ */
202 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */
203 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */
222 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */
223 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */
224 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */
225 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */
226 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */
227 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */
228 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */
229 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */
230 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */
231 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */
241 EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */
247 TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */
248 TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */
249 PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */
250 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */
251 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */
252 DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */
253 DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */
254 PA_MASK_EN, /* IPA v4.0+ */
255 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */
256 DUAL_TX_ENABLE, /* IPA v4.5+ */
257 SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */
258 SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */
259 HOLB_STICKY_DROP_EN, /* IPA v5.0+ */
278 DPL_TIMESTAMP_LSB, /* Not IPA v5.5+ */
279 DPL_TIMESTAMP_SEL, /* Not IPA v5.5+ */
320 ENDP_SUSPEND, /* Not IPA v4.0+ */
321 ENDP_DELAY, /* Not IPA v4.2+ */
330 PIPE_REPLICATE_EN, /* IPA v5.5+ */
336 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */
337 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */
338 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */
361 HDR_A5_MUX, /* Not IPA v4.9+ */
363 HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */
364 HDR_LEN_MSB, /* IPA v4.5+ */
365 HDR_OFST_METADATA_MSB, /* IPA v4.5+ */
376 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */
377 HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */
378 HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */
379 HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */
380 HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */
386 DCPH_ENABLE, /* IPA v4.5+ */
389 PIPE_REPLICATION_EN, /* Not IPA v5.5+ */
391 HDR_FTCH_DISABLE, /* IPA v4.5+ */
392 DRBIP_ACL_ENABLE, /* IPA v4.9+ */
414 AGGR_COAL_L2, /* IPA v5.5+ */
442 TIMER_BASE_VALUE, /* Not IPA v4.5+ */
443 TIMER_SCALE, /* IPA v4.2 only */
444 TIMER_LIMIT, /* IPA v4.5+ */
445 TIMER_GRAN_SEL, /* IPA v4.5+ */
466 SEQ_REP_TYPE, /* Not IPA v4.5+ */
480 * passes a packet takes through the IPA pipeline. The last pass through can
515 STATUS_LOCATION, /* Not IPA v4.5+ */
516 STATUS_PKT_SUPPRESS, /* IPA v4.0+ */
553 * enum ipa_irq_id - Bit positions representing type of IPA IRQ
592 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, /* Not IPA v5.5+ */
593 IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */
601 IPA_IRQ_RX_ERR = 0x9, /* Not IPA v5.5+ */
602 IPA_IRQ_DEAGGR_ERR = 0xa, /* Not IPA v5.5+ */
603 IPA_IRQ_TX_ERR = 0xb, /* Not IPA v5.5+ */
604 IPA_IRQ_STEP_MODE = 0xc, /* Not IPA v5.5+ */
605 IPA_IRQ_PROC_ERR = 0xd, /* Not IPA v5.5+ */
614 IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */
618 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5-v5.2 */
619 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9-v5.2 */
620 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9-v5.2 */
621 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9-v5.2 */
622 IPA_IRQ_ERROR_NON_FATAL = 0x1e, /* IPA v5.5+ */
623 IPA_IRQ_ERROR_FATAL = 0x1f, /* IPA v5.5+ */
642 const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);
644 int ipa_reg_init(struct ipa *ipa, struct platform_device *pdev);
645 void ipa_reg_exit(struct ipa *ipa);