Lines Matching +full:global +full:- +full:halt
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2024 Linaro Ltd.
29 * providing a well-defined communication layer between the AP subsystem
32 * -------- ---------
34 * | AP +<---. .----+ Modem |
35 * | +--. | | .->+ |
37 * -------- | | | | ---------
39 * --+-+---+-+--
41 * |-----------|
45 * -------------
53 * with a DRAM-resident array of "transfer elements" (TREs) available to
58 * Each TRE refers to a block of data--also located in DRAM. After writing
83 * Note that all GSI registers are little-endian, which is the assumed
113 /** gsi_channel_scratch_gpi - GPI protocol scratch register
132 /** gsi_channel_scratch - channel scratch configuration area
134 * The exact interpretation of this register is protocol-specific.
169 return channel - &channel->gsi->channel[0]; in gsi_channel_id()
172 /* An initialized channel has a non-null GSI pointer */
175 return !!channel->gsi; in gsi_channel_initialized()
199 gsi->type_enabled_bitmap = val; in gsi_irq_type_update()
200 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_type_update()
205 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | type_id); in gsi_irq_type_enable()
210 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~type_id); in gsi_irq_type_disable()
228 iowrite32(~0, gsi->virt + reg_offset(reg)); in gsi_irq_ev_ctrl_enable()
231 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ev_ctrl_enable()
243 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_ev_ctrl_disable()
261 iowrite32(~0, gsi->virt + reg_offset(reg)); in gsi_irq_ch_ctrl_enable()
264 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ch_ctrl_enable()
277 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_ch_ctrl_disable()
282 bool enable_ieob = !gsi->ieob_enabled_bitmap; in gsi_irq_ieob_enable_one()
286 gsi->ieob_enabled_bitmap |= BIT(evt_ring_id); in gsi_irq_ieob_enable_one()
289 val = gsi->ieob_enabled_bitmap; in gsi_irq_ieob_enable_one()
290 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ieob_enable_one()
302 gsi->ieob_enabled_bitmap &= ~event_mask; in gsi_irq_ieob_disable()
305 if (!gsi->ieob_enabled_bitmap) in gsi_irq_ieob_disable()
309 val = gsi->ieob_enabled_bitmap; in gsi_irq_ieob_disable()
310 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_ieob_disable()
324 /* Global interrupts include hardware error reports. Enable in gsi_irq_enable()
328 iowrite32(ERROR_INT, gsi->virt + reg_offset(reg)); in gsi_irq_enable()
330 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GLOB_EE); in gsi_irq_enable()
341 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_irq_enable()
343 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | GSI_GENERAL); in gsi_irq_enable()
353 /* Clear the type-specific interrupt masks set by gsi_irq_enable() */ in gsi_irq_disable()
355 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_disable()
358 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_disable()
365 return ring->virt + (index % ring->count) * GSI_RING_ELEMENT_SIZE; in gsi_ring_virt()
368 /* Return the 32-bit DMA address associated with a ring index */
371 return lower_32_bits(ring->addr) + index * GSI_RING_ELEMENT_SIZE; in gsi_ring_addr()
374 /* Return the ring index of a 32-bit ring offset */
377 return (offset - gsi_ring_addr(ring, 0)) / GSI_RING_ELEMENT_SIZE; in gsi_ring_index()
387 struct completion *completion = &gsi->completion; in gsi_command()
391 iowrite32(val, gsi->virt + reg); in gsi_command()
403 val = ioread32(gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_state()
412 struct device *dev = gsi->dev; in gsi_evt_ring_command()
443 dev_err(gsi->dev, "event ring %u bad state %u before alloc\n", in gsi_evt_ring_alloc_command()
445 return -EINVAL; in gsi_evt_ring_alloc_command()
455 dev_err(gsi->dev, "event ring %u bad state %u after alloc\n", in gsi_evt_ring_alloc_command()
458 return -EIO; in gsi_evt_ring_alloc_command()
469 dev_err(gsi->dev, "event ring %u bad state %u before reset\n", in gsi_evt_ring_reset_command()
481 dev_err(gsi->dev, "event ring %u bad state %u after reset\n", in gsi_evt_ring_reset_command()
485 /* Issue a hardware de-allocation request for an allocated event ring */
492 dev_err(gsi->dev, "event ring %u state %u before dealloc\n", in gsi_evt_ring_de_alloc_command()
504 dev_err(gsi->dev, "event ring %u bad state %u after dealloc\n", in gsi_evt_ring_de_alloc_command()
511 const struct reg *reg = gsi_reg(channel->gsi, CH_C_CNTXT_0); in gsi_channel_state()
513 struct gsi *gsi = channel->gsi; in gsi_channel_state()
514 void __iomem *virt = gsi->virt; in gsi_channel_state()
528 struct gsi *gsi = channel->gsi; in gsi_channel_command()
529 struct device *dev = gsi->dev; in gsi_channel_command()
555 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_alloc_command()
556 struct device *dev = gsi->dev; in gsi_channel_alloc_command()
564 return -EINVAL; in gsi_channel_alloc_command()
577 return -EIO; in gsi_channel_alloc_command()
583 struct device *dev = channel->gsi->dev; in gsi_channel_start_command()
591 return -EINVAL; in gsi_channel_start_command()
604 return -EIO; in gsi_channel_start_command()
610 struct device *dev = channel->gsi->dev; in gsi_channel_stop_command()
625 return -EINVAL; in gsi_channel_stop_command()
637 return -EAGAIN; in gsi_channel_stop_command()
642 return -EIO; in gsi_channel_stop_command()
648 struct device *dev = channel->gsi->dev; in gsi_channel_reset_command()
676 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_de_alloc_command()
677 struct device *dev = gsi->dev; in gsi_channel_de_alloc_command()
705 struct gsi_ring *ring = &gsi->evt_ring[evt_ring_id].ring; in gsi_evt_ring_doorbell()
708 ring->index = index; /* Next unused entry */ in gsi_evt_ring_doorbell()
711 val = gsi_ring_addr(ring, (index - 1) % ring->count); in gsi_evt_ring_doorbell()
712 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_doorbell()
718 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_evt_ring_program()
719 struct gsi_ring *ring = &evt_ring->ring; in gsi_evt_ring_program()
729 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
732 val = reg_encode(reg, R_LENGTH, ring->count * GSI_RING_ELEMENT_SIZE); in gsi_evt_ring_program()
733 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
735 /* The context 2 and 3 registers store the low-order and in gsi_evt_ring_program()
736 * high-order 32 bits of the address of the event ring, in gsi_evt_ring_program()
740 val = lower_32_bits(ring->addr); in gsi_evt_ring_program()
741 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
744 val = upper_32_bits(ring->addr); in gsi_evt_ring_program()
745 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
751 /* EV_MOD_CNT is 0 (no counter-based interrupt coalescing) */ in gsi_evt_ring_program()
752 iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
756 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
759 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
762 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
766 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
769 iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id)); in gsi_evt_ring_program()
772 gsi_evt_ring_doorbell(gsi, evt_ring_id, ring->index); in gsi_evt_ring_program()
778 struct gsi_trans_info *trans_info = &channel->trans_info; in gsi_channel_trans_last()
779 u32 pending_id = trans_info->pending_id; in gsi_channel_trans_last()
783 if (channel->toward_ipa && pending_id != trans_info->free_id) { in gsi_channel_trans_last()
789 trans_id = trans_info->free_id - 1; in gsi_channel_trans_last()
790 } else if (trans_info->polled_id != pending_id) { in gsi_channel_trans_last()
797 trans_id = pending_id - 1; in gsi_channel_trans_last()
803 trans = &trans_info->trans[trans_id % channel->tre_count]; in gsi_channel_trans_last()
804 refcount_inc(&trans->refcount); in gsi_channel_trans_last()
817 wait_for_completion(&trans->completion); in gsi_channel_trans_quiesce()
825 size_t size = channel->tre_ring.count * GSI_RING_ELEMENT_SIZE; in gsi_channel_program()
829 struct gsi *gsi = channel->gsi; in gsi_channel_program()
838 val = ch_c_cntxt_0_type_encode(gsi->version, reg, GSI_CHANNEL_TYPE_GPI); in gsi_channel_program()
839 if (channel->toward_ipa) in gsi_channel_program()
841 if (gsi->version < IPA_VERSION_5_0) in gsi_channel_program()
842 val |= reg_encode(reg, ERINDEX, channel->evt_ring_id); in gsi_channel_program()
844 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
848 if (gsi->version >= IPA_VERSION_5_0) in gsi_channel_program()
849 val |= reg_encode(reg, CH_ERINDEX, channel->evt_ring_id); in gsi_channel_program()
850 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
852 /* The context 2 and 3 registers store the low-order and in gsi_channel_program()
853 * high-order 32 bits of the address of the channel ring, in gsi_channel_program()
857 val = lower_32_bits(channel->tre_ring.addr); in gsi_channel_program()
858 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
861 val = upper_32_bits(channel->tre_ring.addr); in gsi_channel_program()
862 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
866 /* Command channel gets low weighted round-robin priority */ in gsi_channel_program()
867 if (channel->command) in gsi_channel_program()
874 if (gsi->version < IPA_VERSION_4_0 && doorbell) in gsi_channel_program()
880 if (gsi->version >= IPA_VERSION_4_0 && !channel->command) { in gsi_channel_program()
882 if (gsi->version < IPA_VERSION_4_5) in gsi_channel_program()
888 if (gsi->version >= IPA_VERSION_4_9) in gsi_channel_program()
891 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
895 gpi->max_outstanding_tre = channel->trans_tre_max * in gsi_channel_program()
897 gpi->outstanding_threshold = 2 * GSI_RING_ELEMENT_SIZE; in gsi_channel_program()
901 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
905 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
909 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_program()
917 val = ioread32(gsi->virt + offset); in gsi_channel_program()
919 iowrite32(val, gsi->virt + offset); in gsi_channel_program()
926 struct gsi *gsi = channel->gsi; in __gsi_channel_start()
930 if (resume && gsi->version < IPA_VERSION_4_0) in __gsi_channel_start()
933 mutex_lock(&gsi->mutex); in __gsi_channel_start()
937 mutex_unlock(&gsi->mutex); in __gsi_channel_start()
945 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_start()
949 napi_enable(&channel->napi); in gsi_channel_start()
950 gsi_irq_ieob_enable_one(gsi, channel->evt_ring_id); in gsi_channel_start()
954 gsi_irq_ieob_disable_one(gsi, channel->evt_ring_id); in gsi_channel_start()
955 napi_disable(&channel->napi); in gsi_channel_start()
968 if (ret != -EAGAIN) in gsi_channel_stop_retry()
971 } while (retries--); in gsi_channel_stop_retry()
978 struct gsi *gsi = channel->gsi; in __gsi_channel_stop()
985 if (suspend && gsi->version < IPA_VERSION_4_0) in __gsi_channel_stop()
988 mutex_lock(&gsi->mutex); in __gsi_channel_stop()
992 mutex_unlock(&gsi->mutex); in __gsi_channel_stop()
1000 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_stop()
1008 gsi_irq_ieob_disable_one(gsi, channel->evt_ring_id); in gsi_channel_stop()
1009 napi_disable(&channel->napi); in gsi_channel_stop()
1017 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_reset()
1019 mutex_lock(&gsi->mutex); in gsi_channel_reset()
1023 if (gsi->version < IPA_VERSION_4_0 && !channel->toward_ipa) in gsi_channel_reset()
1027 channel->tre_ring.index = 0; in gsi_channel_reset()
1031 mutex_unlock(&gsi->mutex); in gsi_channel_reset()
1037 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_suspend()
1045 napi_synchronize(&channel->napi); in gsi_channel_suspend()
1053 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_resume()
1061 disable_irq(gsi->irq); in gsi_suspend()
1067 enable_irq(gsi->irq); in gsi_resume()
1072 struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id]; in gsi_trans_tx_committed()
1074 channel->trans_count++; in gsi_trans_tx_committed()
1075 channel->byte_count += trans->len; in gsi_trans_tx_committed()
1077 trans->trans_count = channel->trans_count; in gsi_trans_tx_committed()
1078 trans->byte_count = channel->byte_count; in gsi_trans_tx_committed()
1083 u32 channel_id = trans->channel_id; in gsi_trans_tx_queued()
1084 struct gsi *gsi = trans->gsi; in gsi_trans_tx_queued()
1089 channel = &gsi->channel[channel_id]; in gsi_trans_tx_queued()
1091 byte_count = channel->byte_count - channel->queued_byte_count; in gsi_trans_tx_queued()
1092 trans_count = channel->trans_count - channel->queued_trans_count; in gsi_trans_tx_queued()
1093 channel->queued_byte_count = channel->byte_count; in gsi_trans_tx_queued()
1094 channel->queued_trans_count = channel->trans_count; in gsi_trans_tx_queued()
1100 * gsi_trans_tx_completed() - Report completed TX transactions
1116 u32 channel_id = trans->channel_id; in gsi_trans_tx_completed()
1117 struct gsi *gsi = trans->gsi; in gsi_trans_tx_completed()
1122 channel = &gsi->channel[channel_id]; in gsi_trans_tx_completed()
1123 trans_count = trans->trans_count - channel->compl_trans_count; in gsi_trans_tx_completed()
1124 byte_count = trans->byte_count - channel->compl_byte_count; in gsi_trans_tx_completed()
1126 channel->compl_trans_count += trans_count; in gsi_trans_tx_completed()
1127 channel->compl_byte_count += byte_count; in gsi_trans_tx_completed()
1139 channel_mask = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_chan_ctrl()
1142 iowrite32(channel_mask, gsi->virt + reg_offset(reg)); in gsi_isr_chan_ctrl()
1149 complete(&gsi->completion); in gsi_isr_chan_ctrl()
1160 event_mask = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_evt_ctrl()
1163 iowrite32(event_mask, gsi->virt + reg_offset(reg)); in gsi_isr_evt_ctrl()
1170 complete(&gsi->completion); in gsi_isr_evt_ctrl()
1174 /* Global channel error interrupt handler */
1179 dev_err(gsi->dev, "channel %u out of resources\n", channel_id); in gsi_isr_glob_chan_err()
1180 complete(&gsi->completion); in gsi_isr_glob_chan_err()
1185 dev_err(gsi->dev, "channel %u global error ee 0x%08x code 0x%08x\n", in gsi_isr_glob_chan_err()
1189 /* Global event error interrupt handler */
1194 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_isr_glob_evt_err()
1195 u32 channel_id = gsi_channel_id(evt_ring->channel); in gsi_isr_glob_evt_err()
1197 complete(&gsi->completion); in gsi_isr_glob_evt_err()
1198 dev_err(gsi->dev, "evt_ring for channel %u out of resources\n", in gsi_isr_glob_evt_err()
1204 dev_err(gsi->dev, "event ring %u global error ee %u code 0x%08x\n", in gsi_isr_glob_evt_err()
1208 /* Global error interrupt handler */
1223 val = ioread32(gsi->virt + offset); in gsi_isr_glob_err()
1224 iowrite32(0, gsi->virt + offset); in gsi_isr_glob_err()
1227 iowrite32(~0, gsi->virt + reg_offset(clr_reg)); in gsi_isr_glob_err()
1240 dev_err(gsi->dev, "unexpected global error 0x%08x\n", type); in gsi_isr_glob_err()
1251 * commands. We use these to allocate and halt channels on the in gsi_isr_gp_int1()
1259 * It is recommended that we halt the modem channels we allocated in gsi_isr_gp_int1()
1261 * at the time we issue the HALT command. We'll get an error in in gsi_isr_gp_int1()
1270 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_gp_int1()
1276 gsi->result = 0; in gsi_isr_gp_int1()
1280 gsi->result = -EAGAIN; in gsi_isr_gp_int1()
1284 dev_err(gsi->dev, "global INT1 generic result %u\n", result); in gsi_isr_gp_int1()
1285 gsi->result = -EIO; in gsi_isr_gp_int1()
1289 complete(&gsi->completion); in gsi_isr_gp_int1()
1292 /* Inter-EE interrupt handler */
1299 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_glob_ee()
1305 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_isr_glob_ee()
1315 dev_err(gsi->dev, "unexpected global interrupt 0x%08x\n", val); in gsi_isr_glob_ee()
1325 event_mask = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_ieob()
1330 iowrite32(event_mask, gsi->virt + reg_offset(reg)); in gsi_isr_ieob()
1337 napi_schedule(&gsi->evt_ring[evt_ring_id].channel->napi); in gsi_isr_ieob()
1344 struct device *dev = gsi->dev; in gsi_isr_general()
1349 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_isr_general()
1352 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_isr_general()
1358 * gsi_isr() - Top level GSI interrupt service routine
1377 while ((intr_mask = ioread32(gsi->virt + offset))) { in gsi_isr()
1385 * when the type-specific register is updated. in gsi_isr()
1404 dev_err(gsi->dev, in gsi_isr()
1412 dev_err(gsi->dev, "interrupt flood\n"); in gsi_isr()
1427 return ret ? : -EINVAL; in gsi_irq_init()
1429 gsi->irq = ret; in gsi_irq_init()
1438 u32 channel_id = event->chid; in gsi_event_trans()
1444 channel = &gsi->channel[channel_id]; in gsi_event_trans()
1445 if (WARN(!channel->gsi, "event has bad channel %u\n", channel_id)) in gsi_event_trans()
1449 tre_offset = lower_32_bits(le64_to_cpu(event->xfer_ptr)); in gsi_event_trans()
1450 tre_index = gsi_ring_index(&channel->tre_ring, tre_offset); in gsi_event_trans()
1461 * gsi_evt_ring_update() - Update transaction state from hardware
1486 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_evt_ring_update()
1487 struct gsi_ring *ring = &evt_ring->ring; in gsi_evt_ring_update()
1493 /* Starting with the oldest un-processed event, determine which in gsi_evt_ring_update()
1500 old_index = ring->index; in gsi_evt_ring_update()
1506 event_avail = ring->count - old_index % ring->count; in gsi_evt_ring_update()
1515 if (trans->direction == DMA_FROM_DEVICE) in gsi_evt_ring_update()
1516 trans->len = __le16_to_cpu(event->len); in gsi_evt_ring_update()
1523 if (--event_avail) in gsi_evt_ring_update()
1537 struct device *dev = gsi->dev; in gsi_ring_alloc()
1542 * be a power-of-2 number of pages, which satisfies the requirement. in gsi_ring_alloc()
1544 ring->virt = dma_alloc_coherent(dev, size, &addr, GFP_KERNEL); in gsi_ring_alloc()
1545 if (!ring->virt) in gsi_ring_alloc()
1546 return -ENOMEM; in gsi_ring_alloc()
1548 ring->addr = addr; in gsi_ring_alloc()
1549 ring->count = count; in gsi_ring_alloc()
1550 ring->index = 0; in gsi_ring_alloc()
1555 /* Free a previously-allocated ring */
1558 size_t size = ring->count * GSI_RING_ELEMENT_SIZE; in gsi_ring_free()
1560 dma_free_coherent(gsi->dev, size, ring->virt, ring->addr); in gsi_ring_free()
1568 if (gsi->event_bitmap == ~0U) { in gsi_evt_ring_id_alloc()
1569 dev_err(gsi->dev, "event rings exhausted\n"); in gsi_evt_ring_id_alloc()
1570 return -ENOSPC; in gsi_evt_ring_id_alloc()
1573 evt_ring_id = ffz(gsi->event_bitmap); in gsi_evt_ring_id_alloc()
1574 gsi->event_bitmap |= BIT(evt_ring_id); in gsi_evt_ring_id_alloc()
1579 /* Free a previously-allocated event ring id */
1582 gsi->event_bitmap &= ~BIT(evt_ring_id); in gsi_evt_ring_id_free()
1585 /* Ring a channel doorbell, reporting the first un-filled entry */
1588 struct gsi_ring *tre_ring = &channel->tre_ring; in gsi_channel_doorbell()
1590 struct gsi *gsi = channel->gsi; in gsi_channel_doorbell()
1596 val = gsi_ring_addr(tre_ring, tre_ring->index % tre_ring->count); in gsi_channel_doorbell()
1597 iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); in gsi_channel_doorbell()
1603 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_update()
1604 struct gsi *gsi = channel->gsi; in gsi_channel_update()
1612 evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_channel_update()
1613 ring = &evt_ring->ring; in gsi_channel_update()
1620 index = gsi_ring_index(ring, ioread32(gsi->virt + offset)); in gsi_channel_update()
1621 if (index == ring->index % ring->count) in gsi_channel_update()
1625 trans = gsi_event_trans(gsi, gsi_ring_virt(ring, index - 1)); in gsi_channel_update()
1638 * gsi_channel_poll_one() - Return a single completed transaction on a channel
1662 * gsi_channel_poll() - NAPI poll function for a channel
1689 gsi_irq_ieob_enable_one(channel->gsi, channel->evt_ring_id); in gsi_channel_poll()
1701 u32 event_bitmap = GENMASK(BITS_PER_LONG - 1, evt_ring_max); in gsi_event_bitmap_init()
1711 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_setup_one()
1712 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_setup_one()
1730 if (channel->toward_ipa) in gsi_channel_setup_one()
1731 netif_napi_add_tx(gsi->dummy_dev, &channel->napi, in gsi_channel_setup_one()
1734 netif_napi_add(gsi->dummy_dev, &channel->napi, in gsi_channel_setup_one()
1749 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_teardown_one()
1750 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_teardown_one()
1755 netif_napi_del(&channel->napi); in gsi_channel_teardown_one()
1775 /* The error global interrupt type is always enabled (until we tear in gsi_generic_command()
1778 * A generic EE command completes with a GSI global interrupt of in gsi_generic_command()
1780 * (to allocate, halt, or enable/disable flow control on a modem in gsi_generic_command()
1786 iowrite32(val, gsi->virt + reg_offset(reg)); in gsi_generic_command()
1791 val = ioread32(gsi->virt + offset); in gsi_generic_command()
1794 iowrite32(val, gsi->virt + offset); in gsi_generic_command()
1801 if (gsi->version >= IPA_VERSION_4_11) in gsi_generic_command()
1808 iowrite32(ERROR_INT, gsi->virt + reg_offset(reg)); in gsi_generic_command()
1811 return gsi->result; in gsi_generic_command()
1813 dev_err(gsi->dev, "GSI generic command %u to channel %u timed out\n", in gsi_generic_command()
1816 return -ETIMEDOUT; in gsi_generic_command()
1833 while (ret == -EAGAIN && retries--); in gsi_modem_channel_halt()
1836 dev_err(gsi->dev, "error %d halting modem channel %u\n", in gsi_modem_channel_halt()
1850 /* Disabling flow control on IPA v4.11+ can return -EAGAIN if enable in gsi_modem_channel_flow_control()
1853 if (!enable && gsi->version >= IPA_VERSION_4_11) in gsi_modem_channel_flow_control()
1858 while (ret == -EAGAIN && retries--); in gsi_modem_channel_flow_control()
1861 dev_err(gsi->dev, in gsi_modem_channel_flow_control()
1875 mutex_lock(&gsi->mutex); in gsi_channel_setup()
1881 } while (++channel_id < gsi->channel_count); in gsi_channel_setup()
1885 struct gsi_channel *channel = &gsi->channel[channel_id++]; in gsi_channel_setup()
1890 ret = -EINVAL; in gsi_channel_setup()
1891 dev_err(gsi->dev, "channel %u not supported by hardware\n", in gsi_channel_setup()
1892 channel_id - 1); in gsi_channel_setup()
1893 channel_id = gsi->channel_count; in gsi_channel_setup()
1898 mask = gsi->modem_channel_bitmap; in gsi_channel_setup()
1910 mutex_unlock(&gsi->mutex); in gsi_channel_setup()
1916 mask ^= gsi->modem_channel_bitmap; in gsi_channel_setup()
1926 while (channel_id--) in gsi_channel_setup()
1929 mutex_unlock(&gsi->mutex); in gsi_channel_setup()
1939 u32 mask = gsi->modem_channel_bitmap; in gsi_channel_teardown()
1942 mutex_lock(&gsi->mutex); in gsi_channel_teardown()
1952 channel_id = gsi->channel_count - 1; in gsi_channel_teardown()
1955 while (channel_id--); in gsi_channel_teardown()
1957 mutex_unlock(&gsi->mutex); in gsi_channel_teardown()
1970 iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1975 /* Clear all type-specific interrupt masks */ in gsi_irq_setup()
1977 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1980 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1983 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1986 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1988 /* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */ in gsi_irq_setup()
1989 if (gsi->version > IPA_VERSION_3_1) { in gsi_irq_setup()
1991 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1994 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
1998 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_irq_setup()
2000 ret = request_irq(gsi->irq, gsi_isr, 0, "gsi", gsi); in gsi_irq_setup()
2002 dev_err(gsi->dev, "error %d requesting \"gsi\" IRQ\n", ret); in gsi_irq_setup()
2009 free_irq(gsi->irq, gsi); in gsi_irq_teardown()
2015 struct device *dev = gsi->dev; in gsi_ring_setup()
2020 if (gsi->version < IPA_VERSION_3_5_1) { in gsi_ring_setup()
2022 gsi->channel_count = GSI_CHANNEL_COUNT_MAX; in gsi_ring_setup()
2023 gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX; in gsi_ring_setup()
2029 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_ring_setup()
2034 return -EINVAL; in gsi_ring_setup()
2041 gsi->channel_count = count; in gsi_ring_setup()
2043 if (gsi->version < IPA_VERSION_5_0) { in gsi_ring_setup()
2051 return -EINVAL; in gsi_ring_setup()
2059 gsi->evt_ring_count = count; in gsi_ring_setup()
2073 val = ioread32(gsi->virt + reg_offset(reg)); in gsi_setup()
2075 dev_err(gsi->dev, "GSI has not been enabled\n"); in gsi_setup()
2076 return -EIO; in gsi_setup()
2089 iowrite32(0, gsi->virt + reg_offset(reg)); in gsi_setup()
2113 struct gsi *gsi = channel->gsi; in gsi_channel_evt_ring_init()
2120 channel->evt_ring_id = ret; in gsi_channel_evt_ring_init()
2122 evt_ring = &gsi->evt_ring[channel->evt_ring_id]; in gsi_channel_evt_ring_init()
2123 evt_ring->channel = channel; in gsi_channel_evt_ring_init()
2125 ret = gsi_ring_alloc(gsi, &evt_ring->ring, channel->event_count); in gsi_channel_evt_ring_init()
2129 dev_err(gsi->dev, "error %d allocating channel %u event ring\n", in gsi_channel_evt_ring_init()
2132 gsi_evt_ring_id_free(gsi, channel->evt_ring_id); in gsi_channel_evt_ring_init()
2140 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_evt_ring_exit()
2141 struct gsi *gsi = channel->gsi; in gsi_channel_evt_ring_exit()
2144 evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_channel_evt_ring_exit()
2145 gsi_ring_free(gsi, &evt_ring->ring); in gsi_channel_evt_ring_exit()
2153 u32 channel_id = data->channel_id; in gsi_channel_data_valid()
2154 struct device *dev = gsi->dev; in gsi_channel_data_valid()
2163 if (data->ee_id != GSI_EE_AP && data->ee_id != GSI_EE_MODEM) { in gsi_channel_data_valid()
2164 dev_err(dev, "bad EE id %u; not AP or modem\n", data->ee_id); in gsi_channel_data_valid()
2168 if (command && !data->toward_ipa) { in gsi_channel_data_valid()
2173 channel_data = &data->channel; in gsi_channel_data_valid()
2175 if (!channel_data->tlv_count || in gsi_channel_data_valid()
2176 channel_data->tlv_count > GSI_TLV_MAX) { in gsi_channel_data_valid()
2178 channel_id, channel_data->tlv_count, GSI_TLV_MAX); in gsi_channel_data_valid()
2182 if (command && IPA_COMMAND_TRANS_TRE_MAX > channel_data->tlv_count) { in gsi_channel_data_valid()
2185 channel_data->tlv_count); in gsi_channel_data_valid()
2189 /* We have to allow at least one maximally-sized transaction to in gsi_channel_data_valid()
2194 if (channel_data->tre_count < 2 * channel_data->tlv_count - 1) { in gsi_channel_data_valid()
2196 channel_id, channel_data->tlv_count, in gsi_channel_data_valid()
2197 channel_data->tre_count); in gsi_channel_data_valid()
2201 if (!is_power_of_2(channel_data->tre_count)) { in gsi_channel_data_valid()
2203 channel_id, channel_data->tre_count); in gsi_channel_data_valid()
2207 if (!is_power_of_2(channel_data->event_count)) { in gsi_channel_data_valid()
2209 channel_id, channel_data->event_count); in gsi_channel_data_valid()
2226 return -EINVAL; in gsi_channel_init_one()
2229 if (data->channel.tre_count > data->channel.event_count) { in gsi_channel_init_one()
2230 tre_count = data->channel.event_count; in gsi_channel_init_one()
2231 dev_warn(gsi->dev, "channel %u limited to %u TREs\n", in gsi_channel_init_one()
2232 data->channel_id, tre_count); in gsi_channel_init_one()
2234 tre_count = data->channel.tre_count; in gsi_channel_init_one()
2237 channel = &gsi->channel[data->channel_id]; in gsi_channel_init_one()
2240 channel->gsi = gsi; in gsi_channel_init_one()
2241 channel->toward_ipa = data->toward_ipa; in gsi_channel_init_one()
2242 channel->command = command; in gsi_channel_init_one()
2243 channel->trans_tre_max = data->channel.tlv_count; in gsi_channel_init_one()
2244 channel->tre_count = tre_count; in gsi_channel_init_one()
2245 channel->event_count = data->channel.event_count; in gsi_channel_init_one()
2251 ret = gsi_ring_alloc(gsi, &channel->tre_ring, data->channel.tre_count); in gsi_channel_init_one()
2253 dev_err(gsi->dev, "error %d allocating channel %u ring\n", in gsi_channel_init_one()
2254 ret, data->channel_id); in gsi_channel_init_one()
2258 ret = gsi_channel_trans_init(gsi, data->channel_id); in gsi_channel_init_one()
2263 u32 tre_max = gsi_channel_tre_max(gsi, data->channel_id); in gsi_channel_init_one()
2272 gsi_ring_free(gsi, &channel->tre_ring); in gsi_channel_init_one()
2276 channel->gsi = NULL; /* Mark it not (fully) initialized */ in gsi_channel_init_one()
2287 if (channel->command) in gsi_channel_exit_one()
2290 gsi_ring_free(channel->gsi, &channel->tre_ring); in gsi_channel_exit_one()
2303 modem_alloc = gsi->version == IPA_VERSION_4_2; in gsi_channel_init()
2305 gsi->event_bitmap = gsi_event_bitmap_init(GSI_EVT_RING_COUNT_MAX); in gsi_channel_init()
2306 gsi->ieob_enabled_bitmap = 0; in gsi_channel_init()
2318 gsi->modem_channel_bitmap |= in gsi_channel_init()
2331 while (i--) { in gsi_channel_init()
2335 gsi->modem_channel_bitmap &= ~BIT(data[i].channel_id); in gsi_channel_init()
2338 gsi_channel_exit_one(&gsi->channel[data->channel_id]); in gsi_channel_init()
2347 u32 channel_id = GSI_CHANNEL_COUNT_MAX - 1; in gsi_channel_exit()
2350 gsi_channel_exit_one(&gsi->channel[channel_id]); in gsi_channel_exit()
2351 while (channel_id--); in gsi_channel_exit()
2352 gsi->modem_channel_bitmap = 0; in gsi_channel_exit()
2364 gsi->dev = &pdev->dev; in gsi_init()
2365 gsi->version = version; in gsi_init()
2370 gsi->dummy_dev = alloc_netdev_dummy(0); in gsi_init()
2371 if (!gsi->dummy_dev) in gsi_init()
2372 return -ENOMEM; in gsi_init()
2373 init_completion(&gsi->completion); in gsi_init()
2387 mutex_init(&gsi->mutex); in gsi_init()
2392 free_netdev(gsi->dummy_dev); in gsi_init()
2401 mutex_destroy(&gsi->mutex); in gsi_exit()
2403 free_netdev(gsi->dummy_dev); in gsi_exit()
2415 * would be (tre_count - 1).
2423 * a pool to avoid crossing that power-of-2 boundary, and this can
2429 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_tre_max()
2431 /* Hardware limit is channel->tre_count - 1 */ in gsi_channel_tre_max()
2432 return channel->tre_count - (channel->trans_tre_max - 1); in gsi_channel_tre_max()