Lines Matching +full:5 +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
169 /*------------------- 0x5C */
170 /*------------------- 0x5D */
185 /*------------------- 0x6C */
186 /*------------------- 0x6D */
191 /*------------------- 0x72 */
192 /*------------------- 0x73 */
195 /*------------------- 0x76 */
196 /*------------------- 0x77 */
209 /*------------------- 0x84 */
210 /*------------------- 0x85 */
212 /*------------------- 0x87 */
213 /*------------------- 0x88 */
216 /*------------------- 0x8B */
217 /*------------------- 0x8C */
220 /*------------------- 0x8F */
221 /*------------------- 0x90 */
224 /*------------------- 0x93 */
225 /*------------------- 0x94 */
230 /*------------------- 0x99 */
239 /*------------------- 0xA2 */
246 /*------------------- 0xA9 */
256 /* IRQSTS1 bits */
259 #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5)
266 /* IRQSTS2 bits */
269 #define DAR_IRQSTS2_SRCADDR BIT(5)
276 /* IRQSTS3 bits */
279 #define DAR_IRQSTS3_TMR2MSK BIT(5)
286 /* PHY_CTRL1 bits */
289 #define DAR_PHY_CTRL1_CCABFRTX BIT(5)
290 #define DAR_PHY_CTRL1_CCABFRTX_SHIFT 5
295 /* PHY_CTRL2 bits */
298 #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5)
305 /* PHY_CTRL3 bits */
308 #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5)
314 /* RX_FRM_LEN bits */
317 /* PHY_CTRL4 bits */
320 #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5)
328 /* SRC_CTRL bits */
336 /* DAR_ASM_CTRL1 bits */
339 #define DAR_ASM_CTRL1_SELFTST BIT(5)
345 /* DAR_ASM_CTRL2 bits */
347 #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT (5)
350 /* DAR_CLK_OUT_CTRL bits */
353 #define DAR_CLK_OUT_CTRL_SR BIT(5)
358 /* DAR_PWR_MODES bits */
359 #define DAR_PWR_MODES_XTAL_READY BIT(5)
365 /* RX_FRAME_FILTER bits */
368 #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5)
375 /* DUAL_PAN_CTRL bits */
383 /* DUAL_PAN_STS bits */
388 /* CCA_CTRL bits */
390 #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5)
397 /* ANT_PAD_CTRL bits */
404 /* MISC_PAD_CTRL bits */
410 /* ANT_AGC_CTRL bits */
416 /* BSM_CTRL bits */
419 /* SOFT_RESET bits */
427 /* SEQ_MGR_CTRL bits */
430 #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5)
437 /* SEQ_MGR_STS bits */
440 #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5)
445 /* ABORT_STS bits */
450 /* IAR_FILTERFAIL_CODE2 bits */
454 /* PHY_STS bits */
457 #define IAR_PHY_STS_PLL_LOCK BIT(5)
463 /* TESTMODE_CTRL bits */
470 /* DTM_CTRL1 bits */
473 #define IAR_DTM_CTRL1_PAGE5 BIT(5)