Lines Matching +full:1 +full:br +full:- +full:10
1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define R1 1
17 #define R10 10
37 /* Write Register 1 */
73 #define SB1 0x4 /* 1 stop bit/char */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
107 #define VIS 1 /* Vector Includes Status */
117 /* Write Register 10 (misc control bits) */
118 #define BIT6 1 /* 6 bit/8bit sync */
125 #define FM1 0x40 /* FM1 (transition = 1) */
131 #define TRxCTC 1 /* TRxC = Transmit clock */
132 #define TRxCBR 2 /* TRxC = BR Generator Output */
137 #define TCBR 0x10 /* Transmit clock = BR Generator output */
141 #define RCBR 0x40 /* Receive clock = BR Generator output */
150 #define BRENABL 1 /* Baud rate generator enable */
158 #define SSBR 0x80 /* Set DPLL source = BR generator */
182 /* Read Register 1 */
191 #define RES18 0xe /* 1/8 */
199 /* Read Register 2 (channel b only) - Interrupt vector */
211 /* Read Register 10 (misc status bits) */
237 #define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */