Lines Matching +full:l +full:- +full:queue
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
41 /* 0x0001 - 0x0003: reserved */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
60 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
63 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
64 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
65 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
66 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
88 * - completely empty (this is the RAP Block window)
106 /* 0x010a - 0x010b: reserved */
112 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
113 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
114 /* 0x0115 - 0x0117: reserved */
117 /* 0x011a - 0x011f: reserved */
122 /* 0x012a - 0x012f: reserved */
127 /* 0x013a - 0x013f: reserved */
146 /* 0x016a - 0x017f: reserved */
174 /* 0x0238 - 0x023f: reserved */
175 /* Receive queue 2 is removed on Monalisa */
189 /* 0x0270 - 0x027c: reserved */
209 /* 0x02b8 - 0x02bc: reserved */
225 /* 0x02f8 - 0x02fc: reserved */
230 /* External PLC-S registers (SN2 compatibility for DV) */
237 /* DAS PLC-S Registers */
240 * Bank 8 - 15
244 /*---------------------------------------------------------------------------*/
298 #define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
299 #define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
300 #define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
301 #define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
303 #define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
305 #define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */
306 #define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */
310 #define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */
311 #define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
312 #define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
313 #define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
314 #define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
315 /* Receive Queue 1 */
316 #define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
317 #define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
318 #define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
319 #define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
320 /* Receive Queue 2 */
321 #define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
322 #define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
323 #define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
324 #define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
325 /* Asynchronous Transmit queue */
327 #define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
328 #define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
329 #define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
330 /* Synchronous Transmit queue */
332 #define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
333 #define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
334 #define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
350 #define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
351 #define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
352 #define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
353 #define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
355 #define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
357 #define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */
358 #define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */
359 #define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */
360 #define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
361 #define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
362 #define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
363 #define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
364 /* Receive Queue 1 */
365 #define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
366 #define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
367 #define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
368 #define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
369 /* Receive Queue 2 */
370 #define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
371 #define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
372 #define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
373 #define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
374 /* Asynchronous Transmit queue */
376 #define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
377 #define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
378 #define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
379 /* Synchronous Transmit queue */
381 #define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
382 #define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
383 #define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
385 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
411 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */
414 /* B2_FDP 8 bit Flash-Prom Data Port */
480 #define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */
484 #define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */
485 #define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */
486 #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/
487 #define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
488 #define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
489 #define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
490 #define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
491 #define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
492 #define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
493 #define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
544 #define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */
545 #define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */
546 #define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */
547 #define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */
548 #define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
549 #define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
550 #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
551 #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
552 #define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */
553 #define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */
554 #define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */
555 #define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */
556 #define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */
557 #define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
559 #define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */
560 #define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */
561 #define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */
562 #define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */
563 #define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
573 #define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */
574 #define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */
575 #define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */
576 #define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/
681 #define BMU_STF (1L<<30) /* Start of Frame ? */
682 #define BMU_EOF (1L<<29) /* End of Frame ? */
683 #define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */
684 #define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */
685 #define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */
686 #define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */
687 #define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */
688 #define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */
689 #define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */
694 * physical address offset + IO-Port base address
697 #define ADDR(a) (char far *) smc->hw.iop+(a)
698 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
700 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
701 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
702 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
703 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
704 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
705 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
759 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
761 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
765 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
768 /*--------------------------------------------------------------------------*/
811 * With SuperNet 3 PHY-A and PHY S are identical.
832 /* read FORMAC+ 32-bit status register */
842 /* read FORMAC+ 32-bit status register */