96 #define xemaclite_readl		ioread32be  macro
99 #define xemaclite_readl		ioread32  macro
155 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_enable_interrupts()
181 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);  in xemaclite_disable_interrupts()
186 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET);  in xemaclite_disable_interrupts()
321 	reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
334 		reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
354 	reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
382 	reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
401 		reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
409 	proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET +  in xemaclite_recv_data()
418 			length = ((ntohl(xemaclite_readl(addr +  in xemaclite_recv_data()
447 	reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
479 	reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);  in xemaclite_update_address()
483 	while ((xemaclite_readl(addr + XEL_TSR_OFFSET) &  in xemaclite_update_address()
646 	if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) &  in xemaclite_interrupt()
648 	    (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)  in xemaclite_interrupt()
654 	tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET);  in xemaclite_interrupt()
664 	tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);  in xemaclite_interrupt()
702 	return readx_poll_timeout(xemaclite_readl,  in xemaclite_mdio_wait()
733 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_read()
743 	rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET);  in xemaclite_mdio_read()
782 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);  in xemaclite_mdio_write()