Lines Matching +full:ethernet +full:- +full:dma
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx Axi Ethernet device driver
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2019 - 2022 Calian Advanced Technologies
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
13 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
19 * - Test and fix basic multicast filtering.
20 * - Add support for extended multicast filtering.
21 * - Test basic VLAN support.
22 * - Add support for extended VLAN support.
42 #include <linux/dma-mapping.h>
43 #include <linux/dma/xilinx_dma.h>
49 /* Descriptors defines for Tx and Rx DMA */
61 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
70 { .compatible = "xlnx,axi-ethernet-1.00.a", },
71 { .compatible = "xlnx,axi-ethernet-1.01.a", },
72 { .compatible = "xlnx,axi-ethernet-2.01.a", },
78 /* Option table for setting up Axi Ethernet hardware options */
135 return lp->rx_skb_ring[i & (RX_BUF_NUM_DEFAULT - 1)]; in axienet_get_rx_desc()
140 return lp->tx_skb_ring[i & (TX_BD_NUM_MAX - 1)]; in axienet_get_tx_desc()
144 * axienet_dma_in32 - Memory mapped Axi DMA register read
146 * @reg: Address offset from the base address of the Axi DMA core
148 * Return: The contents of the Axi DMA register
150 * This function returns the contents of the corresponding Axi DMA register.
154 return ioread32(lp->dma_regs + reg); in axienet_dma_in32()
160 desc->phys = lower_32_bits(addr); in desc_set_phys_addr()
161 if (lp->features & XAE_FEATURE_DMA_64BIT) in desc_set_phys_addr()
162 desc->phys_msb = upper_32_bits(addr); in desc_set_phys_addr()
168 dma_addr_t ret = desc->phys; in desc_get_phys_addr()
170 if (lp->features & XAE_FEATURE_DMA_64BIT) in desc_get_phys_addr()
171 ret |= ((dma_addr_t)desc->phys_msb << 16) << 16; in desc_get_phys_addr()
177 * axienet_dma_bd_release - Release buffer descriptor rings
181 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
189 /* If we end up here, tx_bd_v must have been DMA allocated. */ in axienet_dma_bd_release()
190 dma_free_coherent(lp->dev, in axienet_dma_bd_release()
191 sizeof(*lp->tx_bd_v) * lp->tx_bd_num, in axienet_dma_bd_release()
192 lp->tx_bd_v, in axienet_dma_bd_release()
193 lp->tx_bd_p); in axienet_dma_bd_release()
195 if (!lp->rx_bd_v) in axienet_dma_bd_release()
198 for (i = 0; i < lp->rx_bd_num; i++) { in axienet_dma_bd_release()
204 if (!lp->rx_bd_v[i].skb) in axienet_dma_bd_release()
207 dev_kfree_skb(lp->rx_bd_v[i].skb); in axienet_dma_bd_release()
209 /* For each descriptor, we programmed cntrl with the (non-zero) in axienet_dma_bd_release()
211 * So a non-zero value in there means we need to unmap it. in axienet_dma_bd_release()
213 if (lp->rx_bd_v[i].cntrl) { in axienet_dma_bd_release()
214 phys = desc_get_phys_addr(lp, &lp->rx_bd_v[i]); in axienet_dma_bd_release()
215 dma_unmap_single(lp->dev, phys, in axienet_dma_bd_release()
216 lp->max_frm_size, DMA_FROM_DEVICE); in axienet_dma_bd_release()
220 dma_free_coherent(lp->dev, in axienet_dma_bd_release()
221 sizeof(*lp->rx_bd_v) * lp->rx_bd_num, in axienet_dma_bd_release()
222 lp->rx_bd_v, in axienet_dma_bd_release()
223 lp->rx_bd_p); in axienet_dma_bd_release()
228 if (lp->axi_clk) in axienet_dma_rate()
229 return clk_get_rate(lp->axi_clk); in axienet_dma_rate()
234 * axienet_calc_cr() - Calculate control register value
270 * axienet_coalesce_params() - Extract coalesce parameters from the CR
287 * axienet_dma_start - Set up DMA registers and start DMA operation
292 spin_lock_irq(&lp->rx_cr_lock); in axienet_dma_start()
295 lp->rx_dma_cr &= ~XAXIDMA_CR_RUNSTOP_MASK; in axienet_dma_start()
296 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); in axienet_dma_start()
298 /* Populate the tail pointer and bring the Rx Axi DMA engine out of in axienet_dma_start()
301 axienet_dma_out_addr(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p); in axienet_dma_start()
302 lp->rx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK; in axienet_dma_start()
303 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); in axienet_dma_start()
304 axienet_dma_out_addr(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p + in axienet_dma_start()
305 (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1))); in axienet_dma_start()
306 lp->rx_dma_started = true; in axienet_dma_start()
308 spin_unlock_irq(&lp->rx_cr_lock); in axienet_dma_start()
309 spin_lock_irq(&lp->tx_cr_lock); in axienet_dma_start()
312 lp->tx_dma_cr &= ~XAXIDMA_CR_RUNSTOP_MASK; in axienet_dma_start()
313 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr); in axienet_dma_start()
315 /* Write to the RS (Run-stop) bit in the Tx channel control register. in axienet_dma_start()
319 axienet_dma_out_addr(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p); in axienet_dma_start()
320 lp->tx_dma_cr |= XAXIDMA_CR_RUNSTOP_MASK; in axienet_dma_start()
321 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr); in axienet_dma_start()
322 lp->tx_dma_started = true; in axienet_dma_start()
324 spin_unlock_irq(&lp->tx_cr_lock); in axienet_dma_start()
328 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
331 * Return: 0, on success -ENOMEM, on failure
333 * This function is called to initialize the Rx and Tx DMA descriptor
335 * and is called when Axi Ethernet driver reset is called.
344 lp->tx_bd_ci = 0; in axienet_dma_bd_init()
345 lp->tx_bd_tail = 0; in axienet_dma_bd_init()
346 lp->rx_bd_ci = 0; in axienet_dma_bd_init()
349 lp->tx_bd_v = dma_alloc_coherent(lp->dev, in axienet_dma_bd_init()
350 sizeof(*lp->tx_bd_v) * lp->tx_bd_num, in axienet_dma_bd_init()
351 &lp->tx_bd_p, GFP_KERNEL); in axienet_dma_bd_init()
352 if (!lp->tx_bd_v) in axienet_dma_bd_init()
353 return -ENOMEM; in axienet_dma_bd_init()
355 lp->rx_bd_v = dma_alloc_coherent(lp->dev, in axienet_dma_bd_init()
356 sizeof(*lp->rx_bd_v) * lp->rx_bd_num, in axienet_dma_bd_init()
357 &lp->rx_bd_p, GFP_KERNEL); in axienet_dma_bd_init()
358 if (!lp->rx_bd_v) in axienet_dma_bd_init()
361 for (i = 0; i < lp->tx_bd_num; i++) { in axienet_dma_bd_init()
362 dma_addr_t addr = lp->tx_bd_p + in axienet_dma_bd_init()
363 sizeof(*lp->tx_bd_v) * in axienet_dma_bd_init()
364 ((i + 1) % lp->tx_bd_num); in axienet_dma_bd_init()
366 lp->tx_bd_v[i].next = lower_32_bits(addr); in axienet_dma_bd_init()
367 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_bd_init()
368 lp->tx_bd_v[i].next_msb = upper_32_bits(addr); in axienet_dma_bd_init()
371 for (i = 0; i < lp->rx_bd_num; i++) { in axienet_dma_bd_init()
374 addr = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * in axienet_dma_bd_init()
375 ((i + 1) % lp->rx_bd_num); in axienet_dma_bd_init()
376 lp->rx_bd_v[i].next = lower_32_bits(addr); in axienet_dma_bd_init()
377 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_bd_init()
378 lp->rx_bd_v[i].next_msb = upper_32_bits(addr); in axienet_dma_bd_init()
380 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size); in axienet_dma_bd_init()
384 lp->rx_bd_v[i].skb = skb; in axienet_dma_bd_init()
385 addr = dma_map_single(lp->dev, skb->data, in axienet_dma_bd_init()
386 lp->max_frm_size, DMA_FROM_DEVICE); in axienet_dma_bd_init()
387 if (dma_mapping_error(lp->dev, addr)) { in axienet_dma_bd_init()
388 netdev_err(ndev, "DMA mapping error\n"); in axienet_dma_bd_init()
391 desc_set_phys_addr(lp, addr, &lp->rx_bd_v[i]); in axienet_dma_bd_init()
393 lp->rx_bd_v[i].cntrl = lp->max_frm_size; in axienet_dma_bd_init()
401 return -ENOMEM; in axienet_dma_bd_init()
405 * axienet_set_mac_address - Write the MAC address
409 * This function is called to initialize the MAC address of the Axi Ethernet
419 if (!is_valid_ether_addr(ndev->dev_addr)) in axienet_set_mac_address()
424 (ndev->dev_addr[0]) | in axienet_set_mac_address()
425 (ndev->dev_addr[1] << 8) | in axienet_set_mac_address()
426 (ndev->dev_addr[2] << 16) | in axienet_set_mac_address()
427 (ndev->dev_addr[3] << 24)); in axienet_set_mac_address()
431 (ndev->dev_addr[4] | in axienet_set_mac_address()
432 (ndev->dev_addr[5] << 8)))); in axienet_set_mac_address()
436 * netdev_set_mac_address - Write the MAC address (from outside the driver)
442 * This function is called to initialize the MAC address of the Axi Ethernet
450 axienet_set_mac_address(ndev, addr->sa_data); in netdev_set_mac_address()
455 * axienet_set_multicast_list - Prepare the multicast table
459 * initialization. The Axi Ethernet basic multicast support has a four-entry
473 if (ndev->flags & IFF_PROMISC) in axienet_set_multicast_list()
479 if (ndev->flags & IFF_ALLMULTI || in axienet_set_multicast_list()
496 af0reg = (ha->addr[0]); in axienet_set_multicast_list()
497 af0reg |= (ha->addr[1] << 8); in axienet_set_multicast_list()
498 af0reg |= (ha->addr[2] << 16); in axienet_set_multicast_list()
499 af0reg |= (ha->addr[3] << 24); in axienet_set_multicast_list()
501 af1reg = (ha->addr[4]); in axienet_set_multicast_list()
502 af1reg |= (ha->addr[5] << 8); in axienet_set_multicast_list()
526 * axienet_setoptions - Set an Axi Ethernet option
530 * The Axi Ethernet core has multiple features which can be selectively turned
533 * these options in the Axi Ethernet hardware. This is done through
542 while (tp->opt) { in axienet_setoptions()
543 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or)); in axienet_setoptions()
544 if (options & tp->opt) in axienet_setoptions()
545 reg |= tp->m_or; in axienet_setoptions()
546 axienet_iow(lp, tp->reg, reg); in axienet_setoptions()
550 lp->options |= options; in axienet_setoptions()
557 if (lp->reset_in_progress) in axienet_stat()
558 return lp->hw_stat_base[stat]; in axienet_stat()
561 return lp->hw_stat_base[stat] + (counter - lp->hw_last_counter[stat]); in axienet_stat()
568 write_seqcount_begin(&lp->hw_stats_seqcount); in axienet_stats_update()
569 lp->reset_in_progress = reset; in axienet_stats_update()
573 lp->hw_stat_base[stat] += counter - lp->hw_last_counter[stat]; in axienet_stats_update()
574 lp->hw_last_counter[stat] = counter; in axienet_stats_update()
576 write_seqcount_end(&lp->hw_stats_seqcount); in axienet_stats_update()
584 mutex_lock(&lp->stats_lock); in axienet_refresh_stats()
586 mutex_unlock(&lp->stats_lock); in axienet_refresh_stats()
589 schedule_delayed_work(&lp->stats_work, 13 * HZ); in axienet_refresh_stats()
598 mutex_lock(&lp->stats_lock); in __axienet_device_reset()
599 if (lp->features & XAE_FEATURE_STATS) in __axienet_device_reset()
602 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset in __axienet_device_reset()
603 * process of Axi DMA takes a while to complete as all pending in __axienet_device_reset()
607 * they both reset the entire DMA core, so only one needs to be used. in __axienet_device_reset()
615 dev_err(lp->dev, "%s: DMA reset timeout!\n", __func__); in __axienet_device_reset()
625 dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__); in __axienet_device_reset()
630 if (lp->features & XAE_FEATURE_STATS) { in __axienet_device_reset()
633 write_seqcount_begin(&lp->hw_stats_seqcount); in __axienet_device_reset()
634 lp->reset_in_progress = false; in __axienet_device_reset()
639 lp->hw_stat_base[stat] += in __axienet_device_reset()
640 lp->hw_last_counter[stat] - counter; in __axienet_device_reset()
641 lp->hw_last_counter[stat] = counter; in __axienet_device_reset()
643 write_seqcount_end(&lp->hw_stats_seqcount); in __axienet_device_reset()
647 mutex_unlock(&lp->stats_lock); in __axienet_device_reset()
652 * axienet_dma_stop - Stop DMA operation
660 spin_lock_irq(&lp->rx_cr_lock); in axienet_dma_stop()
662 cr = lp->rx_dma_cr & ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); in axienet_dma_stop()
664 lp->rx_dma_started = false; in axienet_dma_stop()
666 spin_unlock_irq(&lp->rx_cr_lock); in axienet_dma_stop()
667 synchronize_irq(lp->rx_irq); in axienet_dma_stop()
669 spin_lock_irq(&lp->tx_cr_lock); in axienet_dma_stop()
671 cr = lp->tx_dma_cr & ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); in axienet_dma_stop()
673 lp->tx_dma_started = false; in axienet_dma_stop()
675 spin_unlock_irq(&lp->tx_cr_lock); in axienet_dma_stop()
676 synchronize_irq(lp->tx_irq); in axienet_dma_stop()
691 /* Do a reset to ensure DMA is really stopped */ in axienet_dma_stop()
698 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
701 * This function is called to reset and initialize the Axi Ethernet core. This
702 * is typically called during initialization. It does a reset of the Axi DMA
703 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
704 * are connected to Axi Ethernet reset lines, this in turn resets the Axi
705 * Ethernet core. No separate hardware reset is done for the Axi Ethernet
716 lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE; in axienet_device_reset()
717 lp->options |= XAE_OPTION_VLAN; in axienet_device_reset()
718 lp->options &= (~XAE_OPTION_JUMBO); in axienet_device_reset()
720 if (ndev->mtu > XAE_MTU && ndev->mtu <= XAE_JUMBO_MTU) { in axienet_device_reset()
721 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN + in axienet_device_reset()
724 if (lp->max_frm_size <= lp->rxmem) in axienet_device_reset()
725 lp->options |= XAE_OPTION_JUMBO; in axienet_device_reset()
728 if (!lp->use_dmaengine) { in axienet_device_reset()
748 axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? in axienet_device_reset()
756 axienet_setoptions(ndev, lp->options & in axienet_device_reset()
760 axienet_setoptions(ndev, lp->options); in axienet_device_reset()
768 * axienet_free_tx_chain - Clean up a series of linked TX descriptors.
774 * in all cleaned-up descriptors. Ignored if NULL.
791 cur_p = &lp->tx_bd_v[(first_bd + i) % lp->tx_bd_num]; in axienet_free_tx_chain()
792 status = cur_p->status; in axienet_free_tx_chain()
803 dma_unmap_single(lp->dev, phys, in axienet_free_tx_chain()
804 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK), in axienet_free_tx_chain()
807 if (cur_p->skb && (status & XAXIDMA_BD_STS_COMPLETE_MASK)) { in axienet_free_tx_chain()
808 napi_consume_skb(cur_p->skb, budget); in axienet_free_tx_chain()
812 cur_p->app0 = 0; in axienet_free_tx_chain()
813 cur_p->app1 = 0; in axienet_free_tx_chain()
814 cur_p->app2 = 0; in axienet_free_tx_chain()
815 cur_p->app4 = 0; in axienet_free_tx_chain()
816 cur_p->skb = NULL; in axienet_free_tx_chain()
819 cur_p->cntrl = 0; in axienet_free_tx_chain()
820 cur_p->status = 0; in axienet_free_tx_chain()
827 lp->tx_bd_ci += i; in axienet_free_tx_chain()
828 if (lp->tx_bd_ci >= lp->tx_bd_num) in axienet_free_tx_chain()
829 lp->tx_bd_ci %= lp->tx_bd_num; in axienet_free_tx_chain()
836 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
855 cur_p = &lp->tx_bd_v[(READ_ONCE(lp->tx_bd_tail) + num_frag) % in axienet_check_tx_bd_space()
856 lp->tx_bd_num]; in axienet_check_tx_bd_space()
857 if (cur_p->cntrl) in axienet_check_tx_bd_space()
863 * axienet_dma_tx_cb - DMA engine callback for TX channel.
876 skbuf_dma = axienet_get_tx_desc(lp, lp->tx_ring_tail++); in axienet_dma_tx_cb()
877 len = skbuf_dma->skb->len; in axienet_dma_tx_cb()
878 txq = skb_get_tx_queue(lp->ndev, skbuf_dma->skb); in axienet_dma_tx_cb()
879 u64_stats_update_begin(&lp->tx_stat_sync); in axienet_dma_tx_cb()
880 u64_stats_add(&lp->tx_bytes, len); in axienet_dma_tx_cb()
881 u64_stats_add(&lp->tx_packets, 1); in axienet_dma_tx_cb()
882 u64_stats_update_end(&lp->tx_stat_sync); in axienet_dma_tx_cb()
883 dma_unmap_sg(lp->dev, skbuf_dma->sgl, skbuf_dma->sg_len, DMA_TO_DEVICE); in axienet_dma_tx_cb()
884 dev_consume_skb_any(skbuf_dma->skb); in axienet_dma_tx_cb()
886 CIRC_SPACE(lp->tx_ring_head, lp->tx_ring_tail, TX_BD_NUM_MAX), in axienet_dma_tx_cb()
891 * axienet_start_xmit_dmaengine - Starts the transmission.
900 * function sets the skbs, register dma callback API and submit
901 * the dma transaction.
919 dma_dev = lp->tx_chan->device; in axienet_start_xmit_dmaengine()
920 sg_len = skb_shinfo(skb)->nr_frags + 1; in axienet_start_xmit_dmaengine()
921 if (CIRC_SPACE(lp->tx_ring_head, lp->tx_ring_tail, TX_BD_NUM_MAX) <= 1) { in axienet_start_xmit_dmaengine()
928 skbuf_dma = axienet_get_tx_desc(lp, lp->tx_ring_head); in axienet_start_xmit_dmaengine()
932 lp->tx_ring_head++; in axienet_start_xmit_dmaengine()
933 sg_init_table(skbuf_dma->sgl, sg_len); in axienet_start_xmit_dmaengine()
934 ret = skb_to_sgvec(skb, skbuf_dma->sgl, 0, skb->len); in axienet_start_xmit_dmaengine()
938 ret = dma_map_sg(lp->dev, skbuf_dma->sgl, sg_len, DMA_TO_DEVICE); in axienet_start_xmit_dmaengine()
943 if (skb->ip_summed == CHECKSUM_PARTIAL) { in axienet_start_xmit_dmaengine()
944 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) { in axienet_start_xmit_dmaengine()
947 } else if (lp->features & XAE_FEATURE_PARTIAL_TX_CSUM) { in axienet_start_xmit_dmaengine()
949 csum_index_off = csum_start_off + skb->csum_offset; in axienet_start_xmit_dmaengine()
954 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) { in axienet_start_xmit_dmaengine()
958 dma_tx_desc = dma_dev->device_prep_slave_sg(lp->tx_chan, skbuf_dma->sgl, in axienet_start_xmit_dmaengine()
964 skbuf_dma->skb = skb; in axienet_start_xmit_dmaengine()
965 skbuf_dma->sg_len = sg_len; in axienet_start_xmit_dmaengine()
966 dma_tx_desc->callback_param = lp; in axienet_start_xmit_dmaengine()
967 dma_tx_desc->callback_result = axienet_dma_tx_cb; in axienet_start_xmit_dmaengine()
968 txq = skb_get_tx_queue(lp->ndev, skb); in axienet_start_xmit_dmaengine()
969 netdev_tx_sent_queue(txq, skb->len); in axienet_start_xmit_dmaengine()
970 netif_txq_maybe_stop(txq, CIRC_SPACE(lp->tx_ring_head, lp->tx_ring_tail, TX_BD_NUM_MAX), in axienet_start_xmit_dmaengine()
974 dma_async_issue_pending(lp->tx_chan); in axienet_start_xmit_dmaengine()
978 dma_unmap_sg(lp->dev, skbuf_dma->sgl, sg_len, DMA_TO_DEVICE); in axienet_start_xmit_dmaengine()
985 * axienet_tx_poll - Invoked once a transmit is completed by the
986 * Axi DMA Tx channel.
1001 struct net_device *ndev = lp->ndev; in axienet_tx_poll()
1005 packets = axienet_free_tx_chain(lp, lp->tx_bd_ci, lp->tx_bd_num, false, in axienet_tx_poll()
1010 u64_stats_update_begin(&lp->tx_stat_sync); in axienet_tx_poll()
1011 u64_stats_add(&lp->tx_packets, packets); in axienet_tx_poll()
1012 u64_stats_add(&lp->tx_bytes, size); in axienet_tx_poll()
1013 u64_stats_update_end(&lp->tx_stat_sync); in axienet_tx_poll()
1023 /* Re-enable TX completion interrupts. This should in axienet_tx_poll()
1027 spin_lock_irq(&lp->tx_cr_lock); in axienet_tx_poll()
1028 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr); in axienet_tx_poll()
1029 spin_unlock_irq(&lp->tx_cr_lock); in axienet_tx_poll()
1035 * axienet_start_xmit - Starts the transmission.
1060 orig_tail_ptr = lp->tx_bd_tail; in axienet_start_xmit()
1063 num_frag = skb_shinfo(skb)->nr_frags; in axienet_start_xmit()
1064 cur_p = &lp->tx_bd_v[orig_tail_ptr]; in axienet_start_xmit()
1077 if (skb->ip_summed == CHECKSUM_PARTIAL) { in axienet_start_xmit()
1078 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) { in axienet_start_xmit()
1080 cur_p->app0 |= 2; in axienet_start_xmit()
1081 } else if (lp->features & XAE_FEATURE_PARTIAL_TX_CSUM) { in axienet_start_xmit()
1083 csum_index_off = csum_start_off + skb->csum_offset; in axienet_start_xmit()
1085 cur_p->app0 |= 1; in axienet_start_xmit()
1086 cur_p->app1 = (csum_start_off << 16) | csum_index_off; in axienet_start_xmit()
1088 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) { in axienet_start_xmit()
1089 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */ in axienet_start_xmit()
1092 phys = dma_map_single(lp->dev, skb->data, in axienet_start_xmit()
1094 if (unlikely(dma_mapping_error(lp->dev, phys))) { in axienet_start_xmit()
1096 netdev_err(ndev, "TX DMA mapping error\n"); in axienet_start_xmit()
1097 ndev->stats.tx_dropped++; in axienet_start_xmit()
1102 cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK; in axienet_start_xmit()
1105 if (++new_tail_ptr >= lp->tx_bd_num) in axienet_start_xmit()
1107 cur_p = &lp->tx_bd_v[new_tail_ptr]; in axienet_start_xmit()
1108 frag = &skb_shinfo(skb)->frags[ii]; in axienet_start_xmit()
1109 phys = dma_map_single(lp->dev, in axienet_start_xmit()
1113 if (unlikely(dma_mapping_error(lp->dev, phys))) { in axienet_start_xmit()
1115 netdev_err(ndev, "TX DMA mapping error\n"); in axienet_start_xmit()
1116 ndev->stats.tx_dropped++; in axienet_start_xmit()
1123 cur_p->cntrl = skb_frag_size(frag); in axienet_start_xmit()
1126 cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK; in axienet_start_xmit()
1127 cur_p->skb = skb; in axienet_start_xmit()
1129 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * new_tail_ptr; in axienet_start_xmit()
1130 if (++new_tail_ptr >= lp->tx_bd_num) in axienet_start_xmit()
1132 WRITE_ONCE(lp->tx_bd_tail, new_tail_ptr); in axienet_start_xmit()
1133 netdev_sent_queue(ndev, skb->len); in axienet_start_xmit()
1145 /* Space might have just been freed - check again */ in axienet_start_xmit()
1154 * axienet_dma_rx_cb - DMA engine callback for RX channel.
1169 skbuf_dma = axienet_get_rx_desc(lp, lp->rx_ring_tail++); in axienet_dma_rx_cb()
1170 skb = skbuf_dma->skb; in axienet_dma_rx_cb()
1171 app_metadata = dmaengine_desc_get_metadata_ptr(skbuf_dma->desc, &meta_len, in axienet_dma_rx_cb()
1173 dma_unmap_single(lp->dev, skbuf_dma->dma_address, lp->max_frm_size, in axienet_dma_rx_cb()
1178 netdev_err(lp->ndev, "Failed to get RX metadata pointer\n"); in axienet_dma_rx_cb()
1180 lp->ndev->stats.rx_dropped++; in axienet_dma_rx_cb()
1187 skb->protocol = eth_type_trans(skb, lp->ndev); in axienet_dma_rx_cb()
1188 skb->ip_summed = CHECKSUM_NONE; in axienet_dma_rx_cb()
1191 u64_stats_update_begin(&lp->rx_stat_sync); in axienet_dma_rx_cb()
1192 u64_stats_add(&lp->rx_packets, 1); in axienet_dma_rx_cb()
1193 u64_stats_add(&lp->rx_bytes, rx_len); in axienet_dma_rx_cb()
1194 u64_stats_update_end(&lp->rx_stat_sync); in axienet_dma_rx_cb()
1197 for (i = 0; i < CIRC_SPACE(lp->rx_ring_head, lp->rx_ring_tail, in axienet_dma_rx_cb()
1199 axienet_rx_submit_desc(lp->ndev); in axienet_dma_rx_cb()
1200 dma_async_issue_pending(lp->rx_chan); in axienet_dma_rx_cb()
1204 * axienet_rx_poll - Triggered by RX ISR to complete the BD processing.
1221 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; in axienet_rx_poll()
1223 while (packets < budget && (cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) { in axienet_rx_poll()
1229 skb = cur_p->skb; in axienet_rx_poll()
1230 cur_p->skb = NULL; in axienet_rx_poll()
1238 length = cur_p->app4 & 0x0000FFFF; in axienet_rx_poll()
1241 dma_unmap_single(lp->dev, phys, lp->max_frm_size, in axienet_rx_poll()
1245 skb->protocol = eth_type_trans(skb, lp->ndev); in axienet_rx_poll()
1247 skb->ip_summed = CHECKSUM_NONE; in axienet_rx_poll()
1250 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) { in axienet_rx_poll()
1251 csumstatus = (cur_p->app2 & in axienet_rx_poll()
1255 skb->ip_summed = CHECKSUM_UNNECESSARY; in axienet_rx_poll()
1257 } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) { in axienet_rx_poll()
1258 skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF); in axienet_rx_poll()
1259 skb->ip_summed = CHECKSUM_COMPLETE; in axienet_rx_poll()
1268 new_skb = napi_alloc_skb(napi, lp->max_frm_size); in axienet_rx_poll()
1272 phys = dma_map_single(lp->dev, new_skb->data, in axienet_rx_poll()
1273 lp->max_frm_size, in axienet_rx_poll()
1275 if (unlikely(dma_mapping_error(lp->dev, phys))) { in axienet_rx_poll()
1277 netdev_err(lp->ndev, "RX DMA mapping error\n"); in axienet_rx_poll()
1283 cur_p->cntrl = lp->max_frm_size; in axienet_rx_poll()
1284 cur_p->status = 0; in axienet_rx_poll()
1285 cur_p->skb = new_skb; in axienet_rx_poll()
1290 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; in axienet_rx_poll()
1292 if (++lp->rx_bd_ci >= lp->rx_bd_num) in axienet_rx_poll()
1293 lp->rx_bd_ci = 0; in axienet_rx_poll()
1294 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; in axienet_rx_poll()
1297 u64_stats_update_begin(&lp->rx_stat_sync); in axienet_rx_poll()
1298 u64_stats_add(&lp->rx_packets, packets); in axienet_rx_poll()
1299 u64_stats_add(&lp->rx_bytes, size); in axienet_rx_poll()
1300 u64_stats_update_end(&lp->rx_stat_sync); in axienet_rx_poll()
1306 if (READ_ONCE(lp->rx_dim_enabled)) { in axienet_rx_poll()
1310 .pkt_ctr = u64_stats_read(&lp->rx_packets), in axienet_rx_poll()
1311 .byte_ctr = u64_stats_read(&lp->rx_bytes), in axienet_rx_poll()
1312 .event_ctr = READ_ONCE(lp->rx_irqs), in axienet_rx_poll()
1315 net_dim(&lp->rx_dim, &sample); in axienet_rx_poll()
1318 /* Re-enable RX completion interrupts. This should in axienet_rx_poll()
1322 spin_lock_irq(&lp->rx_cr_lock); in axienet_rx_poll()
1323 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr); in axienet_rx_poll()
1324 spin_unlock_irq(&lp->rx_cr_lock); in axienet_rx_poll()
1330 * axienet_tx_irq - Tx Done Isr.
1336 * This is the Axi DMA Tx done Isr. It invokes NAPI polling to complete the
1353 netdev_err(ndev, "DMA Tx error 0x%x\n", status); in axienet_tx_irq()
1355 (lp->tx_bd_v[lp->tx_bd_ci]).phys_msb, in axienet_tx_irq()
1356 (lp->tx_bd_v[lp->tx_bd_ci]).phys); in axienet_tx_irq()
1357 schedule_work(&lp->dma_err_task); in axienet_tx_irq()
1362 if (napi_schedule_prep(&lp->napi_tx)) { in axienet_tx_irq()
1365 spin_lock(&lp->tx_cr_lock); in axienet_tx_irq()
1366 cr = lp->tx_dma_cr; in axienet_tx_irq()
1369 spin_unlock(&lp->tx_cr_lock); in axienet_tx_irq()
1370 __napi_schedule(&lp->napi_tx); in axienet_tx_irq()
1378 * axienet_rx_irq - Rx Isr.
1384 * This is the Axi DMA Rx Isr. It invokes NAPI polling to complete the RX BD
1401 netdev_err(ndev, "DMA Rx error 0x%x\n", status); in axienet_rx_irq()
1403 (lp->rx_bd_v[lp->rx_bd_ci]).phys_msb, in axienet_rx_irq()
1404 (lp->rx_bd_v[lp->rx_bd_ci]).phys); in axienet_rx_irq()
1405 schedule_work(&lp->dma_err_task); in axienet_rx_irq()
1410 WRITE_ONCE(lp->rx_irqs, READ_ONCE(lp->rx_irqs) + 1); in axienet_rx_irq()
1411 if (napi_schedule_prep(&lp->napi_rx)) { in axienet_rx_irq()
1414 spin_lock(&lp->rx_cr_lock); in axienet_rx_irq()
1415 cr = lp->rx_dma_cr; in axienet_rx_irq()
1418 spin_unlock(&lp->rx_cr_lock); in axienet_rx_irq()
1420 __napi_schedule(&lp->napi_rx); in axienet_rx_irq()
1428 * axienet_eth_irq - Ethernet core Isr.
1434 * Handle miscellaneous conditions indicated by Ethernet core IRQ.
1447 ndev->stats.rx_missed_errors++; in axienet_eth_irq()
1450 ndev->stats.rx_dropped++; in axienet_eth_irq()
1459 * axienet_rx_submit_desc - Submit the rx descriptors to dmaengine.
1474 skbuf_dma = axienet_get_rx_desc(lp, lp->rx_ring_head); in axienet_rx_submit_desc()
1478 skb = netdev_alloc_skb(ndev, lp->max_frm_size); in axienet_rx_submit_desc()
1482 sg_init_table(skbuf_dma->sgl, 1); in axienet_rx_submit_desc()
1483 addr = dma_map_single(lp->dev, skb->data, lp->max_frm_size, DMA_FROM_DEVICE); in axienet_rx_submit_desc()
1484 if (unlikely(dma_mapping_error(lp->dev, addr))) { in axienet_rx_submit_desc()
1486 netdev_err(ndev, "DMA mapping error\n"); in axienet_rx_submit_desc()
1489 sg_dma_address(skbuf_dma->sgl) = addr; in axienet_rx_submit_desc()
1490 sg_dma_len(skbuf_dma->sgl) = lp->max_frm_size; in axienet_rx_submit_desc()
1491 dma_rx_desc = dmaengine_prep_slave_sg(lp->rx_chan, skbuf_dma->sgl, in axienet_rx_submit_desc()
1497 skbuf_dma->skb = skb; in axienet_rx_submit_desc()
1498 skbuf_dma->dma_address = sg_dma_address(skbuf_dma->sgl); in axienet_rx_submit_desc()
1499 skbuf_dma->desc = dma_rx_desc; in axienet_rx_submit_desc()
1500 dma_rx_desc->callback_param = lp; in axienet_rx_submit_desc()
1501 dma_rx_desc->callback_result = axienet_dma_rx_cb; in axienet_rx_submit_desc()
1502 lp->rx_ring_head++; in axienet_rx_submit_desc()
1508 dma_unmap_single(lp->dev, addr, lp->max_frm_size, DMA_FROM_DEVICE); in axienet_rx_submit_desc()
1514 * axienet_init_dmaengine - init the dmaengine code.
1518 * non-zero error value on failure
1528 lp->tx_chan = dma_request_chan(lp->dev, "tx_chan0"); in axienet_init_dmaengine()
1529 if (IS_ERR(lp->tx_chan)) { in axienet_init_dmaengine()
1530 dev_err(lp->dev, "No Ethernet DMA (TX) channel found\n"); in axienet_init_dmaengine()
1531 return PTR_ERR(lp->tx_chan); in axienet_init_dmaengine()
1534 lp->rx_chan = dma_request_chan(lp->dev, "rx_chan0"); in axienet_init_dmaengine()
1535 if (IS_ERR(lp->rx_chan)) { in axienet_init_dmaengine()
1536 ret = PTR_ERR(lp->rx_chan); in axienet_init_dmaengine()
1537 dev_err(lp->dev, "No Ethernet DMA (RX) channel found\n"); in axienet_init_dmaengine()
1541 lp->tx_ring_tail = 0; in axienet_init_dmaengine()
1542 lp->tx_ring_head = 0; in axienet_init_dmaengine()
1543 lp->rx_ring_tail = 0; in axienet_init_dmaengine()
1544 lp->rx_ring_head = 0; in axienet_init_dmaengine()
1545 lp->tx_skb_ring = kcalloc(TX_BD_NUM_MAX, sizeof(*lp->tx_skb_ring), in axienet_init_dmaengine()
1547 if (!lp->tx_skb_ring) { in axienet_init_dmaengine()
1548 ret = -ENOMEM; in axienet_init_dmaengine()
1554 ret = -ENOMEM; in axienet_init_dmaengine()
1557 lp->tx_skb_ring[i] = skbuf_dma; in axienet_init_dmaengine()
1560 lp->rx_skb_ring = kcalloc(RX_BUF_NUM_DEFAULT, sizeof(*lp->rx_skb_ring), in axienet_init_dmaengine()
1562 if (!lp->rx_skb_ring) { in axienet_init_dmaengine()
1563 ret = -ENOMEM; in axienet_init_dmaengine()
1569 ret = -ENOMEM; in axienet_init_dmaengine()
1572 lp->rx_skb_ring[i] = skbuf_dma; in axienet_init_dmaengine()
1577 dma_async_issue_pending(lp->rx_chan); in axienet_init_dmaengine()
1583 kfree(lp->rx_skb_ring[i]); in axienet_init_dmaengine()
1584 kfree(lp->rx_skb_ring); in axienet_init_dmaengine()
1587 kfree(lp->tx_skb_ring[i]); in axienet_init_dmaengine()
1588 kfree(lp->tx_skb_ring); in axienet_init_dmaengine()
1590 dma_release_channel(lp->rx_chan); in axienet_init_dmaengine()
1592 dma_release_channel(lp->tx_chan); in axienet_init_dmaengine()
1597 * axienet_init_legacy_dma - init the dma legacy code.
1601 * non-zero error value on failure
1603 * This is the dma initialization code. It also allocates interrupt
1612 /* Enable worker thread for Axi DMA error handling */ in axienet_init_legacy_dma()
1613 lp->stopping = false; in axienet_init_legacy_dma()
1614 INIT_WORK(&lp->dma_err_task, axienet_dma_err_handler); in axienet_init_legacy_dma()
1616 napi_enable(&lp->napi_rx); in axienet_init_legacy_dma()
1617 napi_enable(&lp->napi_tx); in axienet_init_legacy_dma()
1619 /* Enable interrupts for Axi DMA Tx */ in axienet_init_legacy_dma()
1620 ret = request_irq(lp->tx_irq, axienet_tx_irq, IRQF_SHARED, in axienet_init_legacy_dma()
1621 ndev->name, ndev); in axienet_init_legacy_dma()
1624 /* Enable interrupts for Axi DMA Rx */ in axienet_init_legacy_dma()
1625 ret = request_irq(lp->rx_irq, axienet_rx_irq, IRQF_SHARED, in axienet_init_legacy_dma()
1626 ndev->name, ndev); in axienet_init_legacy_dma()
1629 /* Enable interrupts for Axi Ethernet core (if defined) */ in axienet_init_legacy_dma()
1630 if (lp->eth_irq > 0) { in axienet_init_legacy_dma()
1631 ret = request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED, in axienet_init_legacy_dma()
1632 ndev->name, ndev); in axienet_init_legacy_dma()
1640 free_irq(lp->rx_irq, ndev); in axienet_init_legacy_dma()
1642 free_irq(lp->tx_irq, ndev); in axienet_init_legacy_dma()
1644 napi_disable(&lp->napi_tx); in axienet_init_legacy_dma()
1645 napi_disable(&lp->napi_rx); in axienet_init_legacy_dma()
1646 cancel_work_sync(&lp->dma_err_task); in axienet_init_legacy_dma()
1647 dev_err(lp->dev, "request_irq() failed\n"); in axienet_init_legacy_dma()
1652 * axienet_open - Driver open routine.
1656 * non-zero error value on failure
1661 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
1669 /* When we do an Axi Ethernet reset, it resets the complete core in axienet_open()
1677 ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); in axienet_open()
1679 dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); in axienet_open()
1683 phylink_start(lp->phylink); in axienet_open()
1686 schedule_delayed_work(&lp->stats_work, 0); in axienet_open()
1688 if (lp->use_dmaengine) { in axienet_open()
1689 /* Enable interrupts for Axi Ethernet core (if defined) */ in axienet_open()
1690 if (lp->eth_irq > 0) { in axienet_open()
1691 ret = request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED, in axienet_open()
1692 ndev->name, ndev); in axienet_open()
1709 if (lp->eth_irq > 0) in axienet_open()
1710 free_irq(lp->eth_irq, ndev); in axienet_open()
1712 cancel_work_sync(&lp->rx_dim.work); in axienet_open()
1713 cancel_delayed_work_sync(&lp->stats_work); in axienet_open()
1714 phylink_stop(lp->phylink); in axienet_open()
1715 phylink_disconnect_phy(lp->phylink); in axienet_open()
1720 * axienet_stop - Driver stop routine.
1727 * The Axi DMA Tx/Rx BDs are released.
1734 if (!lp->use_dmaengine) { in axienet_stop()
1735 WRITE_ONCE(lp->stopping, true); in axienet_stop()
1736 flush_work(&lp->dma_err_task); in axienet_stop()
1738 napi_disable(&lp->napi_tx); in axienet_stop()
1739 napi_disable(&lp->napi_rx); in axienet_stop()
1742 cancel_work_sync(&lp->rx_dim.work); in axienet_stop()
1743 cancel_delayed_work_sync(&lp->stats_work); in axienet_stop()
1745 phylink_stop(lp->phylink); in axienet_stop()
1746 phylink_disconnect_phy(lp->phylink); in axienet_stop()
1748 axienet_setoptions(ndev, lp->options & in axienet_stop()
1751 if (!lp->use_dmaengine) { in axienet_stop()
1753 cancel_work_sync(&lp->dma_err_task); in axienet_stop()
1754 free_irq(lp->tx_irq, ndev); in axienet_stop()
1755 free_irq(lp->rx_irq, ndev); in axienet_stop()
1758 dmaengine_terminate_sync(lp->tx_chan); in axienet_stop()
1759 dmaengine_synchronize(lp->tx_chan); in axienet_stop()
1760 dmaengine_terminate_sync(lp->rx_chan); in axienet_stop()
1761 dmaengine_synchronize(lp->rx_chan); in axienet_stop()
1764 kfree(lp->tx_skb_ring[i]); in axienet_stop()
1765 kfree(lp->tx_skb_ring); in axienet_stop()
1767 kfree(lp->rx_skb_ring[i]); in axienet_stop()
1768 kfree(lp->rx_skb_ring); in axienet_stop()
1770 dma_release_channel(lp->rx_chan); in axienet_stop()
1771 dma_release_channel(lp->tx_chan); in axienet_stop()
1777 if (lp->eth_irq > 0) in axienet_stop()
1778 free_irq(lp->eth_irq, ndev); in axienet_stop()
1783 * axienet_change_mtu - Driver change mtu routine.
1789 * This is the change mtu driver routine. It checks if the Axi Ethernet
1798 return -EBUSY; in axienet_change_mtu()
1801 XAE_TRL_SIZE) > lp->rxmem) in axienet_change_mtu()
1802 return -EINVAL; in axienet_change_mtu()
1804 WRITE_ONCE(ndev->mtu, new_mtu); in axienet_change_mtu()
1811 * axienet_poll_controller - Axi Ethernet poll mechanism.
1821 disable_irq(lp->tx_irq); in axienet_poll_controller()
1822 disable_irq(lp->rx_irq); in axienet_poll_controller()
1823 axienet_rx_irq(lp->tx_irq, ndev); in axienet_poll_controller()
1824 axienet_tx_irq(lp->rx_irq, ndev); in axienet_poll_controller()
1825 enable_irq(lp->tx_irq); in axienet_poll_controller()
1826 enable_irq(lp->rx_irq); in axienet_poll_controller()
1835 return -EINVAL; in axienet_ioctl()
1837 return phylink_mii_ioctl(lp->phylink, rq, cmd); in axienet_ioctl()
1846 netdev_stats_to_stats64(stats, &dev->stats); in axienet_get_stats64()
1849 start = u64_stats_fetch_begin(&lp->rx_stat_sync); in axienet_get_stats64()
1850 stats->rx_packets = u64_stats_read(&lp->rx_packets); in axienet_get_stats64()
1851 stats->rx_bytes = u64_stats_read(&lp->rx_bytes); in axienet_get_stats64()
1852 } while (u64_stats_fetch_retry(&lp->rx_stat_sync, start)); in axienet_get_stats64()
1855 start = u64_stats_fetch_begin(&lp->tx_stat_sync); in axienet_get_stats64()
1856 stats->tx_packets = u64_stats_read(&lp->tx_packets); in axienet_get_stats64()
1857 stats->tx_bytes = u64_stats_read(&lp->tx_bytes); in axienet_get_stats64()
1858 } while (u64_stats_fetch_retry(&lp->tx_stat_sync, start)); in axienet_get_stats64()
1860 if (!(lp->features & XAE_FEATURE_STATS)) in axienet_get_stats64()
1864 start = read_seqcount_begin(&lp->hw_stats_seqcount); in axienet_get_stats64()
1865 stats->rx_length_errors = in axienet_get_stats64()
1867 stats->rx_crc_errors = axienet_stat(lp, STAT_RX_FCS_ERRORS); in axienet_get_stats64()
1868 stats->rx_frame_errors = in axienet_get_stats64()
1870 stats->rx_errors = axienet_stat(lp, STAT_UNDERSIZE_FRAMES) + in axienet_get_stats64()
1872 stats->rx_length_errors + in axienet_get_stats64()
1873 stats->rx_crc_errors + in axienet_get_stats64()
1874 stats->rx_frame_errors; in axienet_get_stats64()
1875 stats->multicast = axienet_stat(lp, STAT_RX_MULTICAST_FRAMES); in axienet_get_stats64()
1877 stats->tx_aborted_errors = in axienet_get_stats64()
1879 stats->tx_fifo_errors = in axienet_get_stats64()
1881 stats->tx_window_errors = in axienet_get_stats64()
1883 stats->tx_errors = axienet_stat(lp, STAT_TX_EXCESS_DEFERRAL) + in axienet_get_stats64()
1884 stats->tx_aborted_errors + in axienet_get_stats64()
1885 stats->tx_fifo_errors + in axienet_get_stats64()
1886 stats->tx_window_errors; in axienet_get_stats64()
1887 } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); in axienet_get_stats64()
1918 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1923 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1928 strscpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); in axienet_ethtools_get_drvinfo()
1929 strscpy(ed->version, DRIVER_VERSION, sizeof(ed->version)); in axienet_ethtools_get_drvinfo()
1933 * axienet_ethtools_get_regs_len - Get the total regs length present in the
1948 * axienet_ethtools_get_regs - Dump the contents of all registers present
1954 * This implements ethtool command for getting the Axi Ethernet register dump.
1955 * Issue "ethtool -d ethX" to execute this function.
1964 regs->version = 0; in axienet_ethtools_get_regs()
1965 regs->len = len; in axienet_ethtools_get_regs()
1996 if (!lp->use_dmaengine) { in axienet_ethtools_get_regs()
2016 ering->rx_max_pending = RX_BD_NUM_MAX; in axienet_ethtools_get_ringparam()
2017 ering->rx_mini_max_pending = 0; in axienet_ethtools_get_ringparam()
2018 ering->rx_jumbo_max_pending = 0; in axienet_ethtools_get_ringparam()
2019 ering->tx_max_pending = TX_BD_NUM_MAX; in axienet_ethtools_get_ringparam()
2020 ering->rx_pending = lp->rx_bd_num; in axienet_ethtools_get_ringparam()
2021 ering->rx_mini_pending = 0; in axienet_ethtools_get_ringparam()
2022 ering->rx_jumbo_pending = 0; in axienet_ethtools_get_ringparam()
2023 ering->tx_pending = lp->tx_bd_num; in axienet_ethtools_get_ringparam()
2034 if (ering->rx_pending > RX_BD_NUM_MAX || in axienet_ethtools_set_ringparam()
2035 ering->rx_mini_pending || in axienet_ethtools_set_ringparam()
2036 ering->rx_jumbo_pending || in axienet_ethtools_set_ringparam()
2037 ering->tx_pending < TX_BD_NUM_MIN || in axienet_ethtools_set_ringparam()
2038 ering->tx_pending > TX_BD_NUM_MAX) in axienet_ethtools_set_ringparam()
2039 return -EINVAL; in axienet_ethtools_set_ringparam()
2042 return -EBUSY; in axienet_ethtools_set_ringparam()
2044 lp->rx_bd_num = ering->rx_pending; in axienet_ethtools_set_ringparam()
2045 lp->tx_bd_num = ering->tx_pending; in axienet_ethtools_set_ringparam()
2050 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
2055 * This implements ethtool command for getting axi ethernet pause frame
2056 * setting. Issue "ethtool -a ethX" to execute this function.
2064 phylink_ethtool_get_pauseparam(lp->phylink, epauseparm); in axienet_ethtools_get_pauseparam()
2068 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
2074 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
2077 * Return: 0 on success, -EFAULT if device is running
2085 return phylink_ethtool_set_pauseparam(lp->phylink, epauseparm); in axienet_ethtools_set_pauseparam()
2089 * axienet_update_coalesce_rx() - Set RX CR
2097 spin_lock_irq(&lp->rx_cr_lock); in axienet_update_coalesce_rx()
2098 lp->rx_dma_cr &= ~mask; in axienet_update_coalesce_rx()
2099 lp->rx_dma_cr |= cr; in axienet_update_coalesce_rx()
2100 /* If DMA isn't started, then the settings will be applied the next in axienet_update_coalesce_rx()
2103 if (lp->rx_dma_started) { in axienet_update_coalesce_rx()
2108 cr = lp->rx_dma_cr; in axienet_update_coalesce_rx()
2110 cr = lp->rx_dma_cr & ~XAXIDMA_IRQ_ALL_MASK; in axienet_update_coalesce_rx()
2113 spin_unlock_irq(&lp->rx_cr_lock); in axienet_update_coalesce_rx()
2117 * axienet_dim_coalesce_count_rx() - RX coalesce count for DIM
2124 return min(1 << (lp->rx_dim.profile_ix << 1), 255); in axienet_dim_coalesce_count_rx()
2128 * axienet_rx_dim_work() - Adjust RX DIM settings
2140 lp->rx_dim.state = DIM_START_MEASURE; in axienet_rx_dim_work()
2144 * axienet_update_coalesce_tx() - Set TX CR
2152 spin_lock_irq(&lp->tx_cr_lock); in axienet_update_coalesce_tx()
2153 lp->tx_dma_cr &= ~mask; in axienet_update_coalesce_tx()
2154 lp->tx_dma_cr |= cr; in axienet_update_coalesce_tx()
2155 /* If DMA isn't started, then the settings will be applied the next in axienet_update_coalesce_tx()
2158 if (lp->tx_dma_started) { in axienet_update_coalesce_tx()
2163 cr = lp->tx_dma_cr; in axienet_update_coalesce_tx()
2165 cr = lp->tx_dma_cr & ~XAXIDMA_IRQ_ALL_MASK; in axienet_update_coalesce_tx()
2168 spin_unlock_irq(&lp->tx_cr_lock); in axienet_update_coalesce_tx()
2172 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
2178 * This implements ethtool command for getting the DMA interrupt coalescing
2179 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
2193 ecoalesce->use_adaptive_rx_coalesce = lp->rx_dim_enabled; in axienet_ethtools_get_coalesce()
2195 spin_lock_irq(&lp->rx_cr_lock); in axienet_ethtools_get_coalesce()
2196 cr = lp->rx_dma_cr; in axienet_ethtools_get_coalesce()
2197 spin_unlock_irq(&lp->rx_cr_lock); in axienet_ethtools_get_coalesce()
2199 &ecoalesce->rx_max_coalesced_frames, in axienet_ethtools_get_coalesce()
2200 &ecoalesce->rx_coalesce_usecs); in axienet_ethtools_get_coalesce()
2202 spin_lock_irq(&lp->tx_cr_lock); in axienet_ethtools_get_coalesce()
2203 cr = lp->tx_dma_cr; in axienet_ethtools_get_coalesce()
2204 spin_unlock_irq(&lp->tx_cr_lock); in axienet_ethtools_get_coalesce()
2206 &ecoalesce->tx_max_coalesced_frames, in axienet_ethtools_get_coalesce()
2207 &ecoalesce->tx_coalesce_usecs); in axienet_ethtools_get_coalesce()
2212 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
2218 * This implements ethtool command for setting the DMA interrupt coalescing
2219 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
2222 * Return: 0, on success, Non-zero error value on failure.
2231 bool new_dim = ecoalesce->use_adaptive_rx_coalesce; in axienet_ethtools_set_coalesce()
2232 bool old_dim = lp->rx_dim_enabled; in axienet_ethtools_set_coalesce()
2235 if (ecoalesce->rx_max_coalesced_frames > 255 || in axienet_ethtools_set_coalesce()
2236 ecoalesce->tx_max_coalesced_frames > 255) { in axienet_ethtools_set_coalesce()
2238 return -EINVAL; in axienet_ethtools_set_coalesce()
2241 if (!ecoalesce->rx_max_coalesced_frames || in axienet_ethtools_set_coalesce()
2242 !ecoalesce->tx_max_coalesced_frames) { in axienet_ethtools_set_coalesce()
2243 NL_SET_ERR_MSG(extack, "frames must be non-zero"); in axienet_ethtools_set_coalesce()
2244 return -EINVAL; in axienet_ethtools_set_coalesce()
2247 if (((ecoalesce->rx_max_coalesced_frames > 1 || new_dim) && in axienet_ethtools_set_coalesce()
2248 !ecoalesce->rx_coalesce_usecs) || in axienet_ethtools_set_coalesce()
2249 (ecoalesce->tx_max_coalesced_frames > 1 && in axienet_ethtools_set_coalesce()
2250 !ecoalesce->tx_coalesce_usecs)) { in axienet_ethtools_set_coalesce()
2252 "usecs must be non-zero when frames is greater than one"); in axienet_ethtools_set_coalesce()
2253 return -EINVAL; in axienet_ethtools_set_coalesce()
2258 ecoalesce->rx_coalesce_usecs); in axienet_ethtools_set_coalesce()
2261 WRITE_ONCE(lp->rx_dim_enabled, false); in axienet_ethtools_set_coalesce()
2262 napi_synchronize(&lp->napi_rx); in axienet_ethtools_set_coalesce()
2263 flush_work(&lp->rx_dim.work); in axienet_ethtools_set_coalesce()
2266 cr = axienet_calc_cr(lp, ecoalesce->rx_max_coalesced_frames, in axienet_ethtools_set_coalesce()
2267 ecoalesce->rx_coalesce_usecs); in axienet_ethtools_set_coalesce()
2270 cr = axienet_calc_cr(lp, 2, ecoalesce->rx_coalesce_usecs); in axienet_ethtools_set_coalesce()
2276 WRITE_ONCE(lp->rx_dim_enabled, true); in axienet_ethtools_set_coalesce()
2278 cr = axienet_calc_cr(lp, ecoalesce->tx_max_coalesced_frames, in axienet_ethtools_set_coalesce()
2279 ecoalesce->tx_coalesce_usecs); in axienet_ethtools_set_coalesce()
2290 return phylink_ethtool_ksettings_get(lp->phylink, cmd); in axienet_ethtools_get_link_ksettings()
2299 return phylink_ethtool_ksettings_set(lp->phylink, cmd); in axienet_ethtools_set_link_ksettings()
2306 return phylink_ethtool_nway_reset(lp->phylink); in axienet_ethtools_nway_reset()
2317 start = read_seqcount_begin(&lp->hw_stats_seqcount); in axienet_ethtools_get_ethtool_stats()
2327 } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); in axienet_ethtools_get_ethtool_stats()
2358 if (lp->features & XAE_FEATURE_STATS) in axienet_ethtools_get_sset_count()
2362 return -EOPNOTSUPP; in axienet_ethtools_get_sset_count()
2373 if (!(lp->features & XAE_FEATURE_STATS)) in axienet_ethtools_get_pause_stats()
2377 start = read_seqcount_begin(&lp->hw_stats_seqcount); in axienet_ethtools_get_pause_stats()
2378 pause_stats->tx_pause_frames = in axienet_ethtools_get_pause_stats()
2380 pause_stats->rx_pause_frames = in axienet_ethtools_get_pause_stats()
2382 } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); in axienet_ethtools_get_pause_stats()
2392 if (!(lp->features & XAE_FEATURE_STATS)) in axienet_ethtool_get_eth_mac_stats()
2396 start = read_seqcount_begin(&lp->hw_stats_seqcount); in axienet_ethtool_get_eth_mac_stats()
2397 mac_stats->FramesTransmittedOK = in axienet_ethtool_get_eth_mac_stats()
2399 mac_stats->SingleCollisionFrames = in axienet_ethtool_get_eth_mac_stats()
2401 mac_stats->MultipleCollisionFrames = in axienet_ethtool_get_eth_mac_stats()
2403 mac_stats->FramesReceivedOK = in axienet_ethtool_get_eth_mac_stats()
2405 mac_stats->FrameCheckSequenceErrors = in axienet_ethtool_get_eth_mac_stats()
2407 mac_stats->AlignmentErrors = in axienet_ethtool_get_eth_mac_stats()
2409 mac_stats->FramesWithDeferredXmissions = in axienet_ethtool_get_eth_mac_stats()
2411 mac_stats->LateCollisions = in axienet_ethtool_get_eth_mac_stats()
2413 mac_stats->FramesAbortedDueToXSColls = in axienet_ethtool_get_eth_mac_stats()
2415 mac_stats->MulticastFramesXmittedOK = in axienet_ethtool_get_eth_mac_stats()
2417 mac_stats->BroadcastFramesXmittedOK = in axienet_ethtool_get_eth_mac_stats()
2419 mac_stats->FramesWithExcessiveDeferral = in axienet_ethtool_get_eth_mac_stats()
2421 mac_stats->MulticastFramesReceivedOK = in axienet_ethtool_get_eth_mac_stats()
2423 mac_stats->BroadcastFramesReceivedOK = in axienet_ethtool_get_eth_mac_stats()
2425 mac_stats->InRangeLengthErrors = in axienet_ethtool_get_eth_mac_stats()
2427 } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); in axienet_ethtool_get_eth_mac_stats()
2437 if (!(lp->features & XAE_FEATURE_STATS)) in axienet_ethtool_get_eth_ctrl_stats()
2441 start = read_seqcount_begin(&lp->hw_stats_seqcount); in axienet_ethtool_get_eth_ctrl_stats()
2442 ctrl_stats->MACControlFramesTransmitted = in axienet_ethtool_get_eth_ctrl_stats()
2444 ctrl_stats->MACControlFramesReceived = in axienet_ethtool_get_eth_ctrl_stats()
2446 ctrl_stats->UnsupportedOpcodesReceived = in axienet_ethtool_get_eth_ctrl_stats()
2448 } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); in axienet_ethtool_get_eth_ctrl_stats()
2470 if (!(lp->features & XAE_FEATURE_STATS)) in axienet_ethtool_get_rmon_stats()
2474 start = read_seqcount_begin(&lp->hw_stats_seqcount); in axienet_ethtool_get_rmon_stats()
2475 rmon_stats->undersize_pkts = in axienet_ethtool_get_rmon_stats()
2477 rmon_stats->oversize_pkts = in axienet_ethtool_get_rmon_stats()
2479 rmon_stats->fragments = in axienet_ethtool_get_rmon_stats()
2482 rmon_stats->hist[0] = in axienet_ethtool_get_rmon_stats()
2484 rmon_stats->hist[1] = in axienet_ethtool_get_rmon_stats()
2486 rmon_stats->hist[2] = in axienet_ethtool_get_rmon_stats()
2488 rmon_stats->hist[3] = in axienet_ethtool_get_rmon_stats()
2490 rmon_stats->hist[4] = in axienet_ethtool_get_rmon_stats()
2492 rmon_stats->hist[5] = in axienet_ethtool_get_rmon_stats()
2494 rmon_stats->hist[6] = in axienet_ethtool_get_rmon_stats()
2495 rmon_stats->oversize_pkts; in axienet_ethtool_get_rmon_stats()
2497 rmon_stats->hist_tx[0] = in axienet_ethtool_get_rmon_stats()
2499 rmon_stats->hist_tx[1] = in axienet_ethtool_get_rmon_stats()
2501 rmon_stats->hist_tx[2] = in axienet_ethtool_get_rmon_stats()
2503 rmon_stats->hist_tx[3] = in axienet_ethtool_get_rmon_stats()
2505 rmon_stats->hist_tx[4] = in axienet_ethtool_get_rmon_stats()
2507 rmon_stats->hist_tx[5] = in axienet_ethtool_get_rmon_stats()
2509 rmon_stats->hist_tx[6] = in axienet_ethtool_get_rmon_stats()
2511 } while (read_seqcount_retry(&lp->hw_stats_seqcount, start)); in axienet_ethtool_get_rmon_stats()
2551 struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy; in axienet_pcs_get_state()
2558 struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy; in axienet_pcs_an_restart()
2568 struct mdio_device *pcs_phy = pcs_to_axienet_local(pcs)->pcs_phy; in axienet_pcs_config()
2569 struct net_device *ndev = pcs_to_axienet_local(pcs)->ndev; in axienet_pcs_config()
2573 if (lp->switch_x_sgmii) { in axienet_pcs_config()
2602 struct net_device *ndev = to_net_dev(config->dev); in axienet_mac_select_pcs()
2607 return &lp->pcs; in axienet_mac_select_pcs()
2631 struct net_device *ndev = to_net_dev(config->dev); in axienet_mac_link_up()
2649 dev_err(&ndev->dev, in axienet_mac_link_up()
2676 * axienet_dma_err_handler - Work queue task for Axi DMA Error
2679 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
2689 struct net_device *ndev = lp->ndev; in axienet_dma_err_handler()
2692 if (READ_ONCE(lp->stopping)) in axienet_dma_err_handler()
2695 napi_disable(&lp->napi_tx); in axienet_dma_err_handler()
2696 napi_disable(&lp->napi_rx); in axienet_dma_err_handler()
2698 axienet_setoptions(ndev, lp->options & in axienet_dma_err_handler()
2704 for (i = 0; i < lp->tx_bd_num; i++) { in axienet_dma_err_handler()
2705 cur_p = &lp->tx_bd_v[i]; in axienet_dma_err_handler()
2706 if (cur_p->cntrl) { in axienet_dma_err_handler()
2709 dma_unmap_single(lp->dev, addr, in axienet_dma_err_handler()
2710 (cur_p->cntrl & in axienet_dma_err_handler()
2714 if (cur_p->skb) in axienet_dma_err_handler()
2715 dev_kfree_skb_irq(cur_p->skb); in axienet_dma_err_handler()
2716 cur_p->phys = 0; in axienet_dma_err_handler()
2717 cur_p->phys_msb = 0; in axienet_dma_err_handler()
2718 cur_p->cntrl = 0; in axienet_dma_err_handler()
2719 cur_p->status = 0; in axienet_dma_err_handler()
2720 cur_p->app0 = 0; in axienet_dma_err_handler()
2721 cur_p->app1 = 0; in axienet_dma_err_handler()
2722 cur_p->app2 = 0; in axienet_dma_err_handler()
2723 cur_p->app3 = 0; in axienet_dma_err_handler()
2724 cur_p->app4 = 0; in axienet_dma_err_handler()
2725 cur_p->skb = NULL; in axienet_dma_err_handler()
2728 for (i = 0; i < lp->rx_bd_num; i++) { in axienet_dma_err_handler()
2729 cur_p = &lp->rx_bd_v[i]; in axienet_dma_err_handler()
2730 cur_p->status = 0; in axienet_dma_err_handler()
2731 cur_p->app0 = 0; in axienet_dma_err_handler()
2732 cur_p->app1 = 0; in axienet_dma_err_handler()
2733 cur_p->app2 = 0; in axienet_dma_err_handler()
2734 cur_p->app3 = 0; in axienet_dma_err_handler()
2735 cur_p->app4 = 0; in axienet_dma_err_handler()
2738 lp->tx_bd_ci = 0; in axienet_dma_err_handler()
2739 lp->tx_bd_tail = 0; in axienet_dma_err_handler()
2740 lp->rx_bd_ci = 0; in axienet_dma_err_handler()
2751 axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? in axienet_dma_err_handler()
2758 axienet_setoptions(ndev, lp->options & in axienet_dma_err_handler()
2762 napi_enable(&lp->napi_rx); in axienet_dma_err_handler()
2763 napi_enable(&lp->napi_tx); in axienet_dma_err_handler()
2764 axienet_setoptions(ndev, lp->options); in axienet_dma_err_handler()
2768 * axienet_probe - Axi Ethernet probe function.
2772 * Non-zero error value on failure.
2774 * This is the probe routine for Axi Ethernet driver. This is called before
2775 * any other driver routines are invoked. It allocates and sets up the Ethernet
2777 * axienet_local. It registers the Ethernet device.
2792 return -ENOMEM; in axienet_probe()
2796 SET_NETDEV_DEV(ndev, &pdev->dev); in axienet_probe()
2797 ndev->features = NETIF_F_SG; in axienet_probe()
2798 ndev->ethtool_ops = &axienet_ethtool_ops; in axienet_probe()
2800 /* MTU range: 64 - 9000 */ in axienet_probe()
2801 ndev->min_mtu = 64; in axienet_probe()
2802 ndev->max_mtu = XAE_JUMBO_MTU; in axienet_probe()
2805 lp->ndev = ndev; in axienet_probe()
2806 lp->dev = &pdev->dev; in axienet_probe()
2807 lp->options = XAE_OPTION_DEFAULTS; in axienet_probe()
2808 lp->rx_bd_num = RX_BD_NUM_DEFAULT; in axienet_probe()
2809 lp->tx_bd_num = TX_BD_NUM_DEFAULT; in axienet_probe()
2811 u64_stats_init(&lp->rx_stat_sync); in axienet_probe()
2812 u64_stats_init(&lp->tx_stat_sync); in axienet_probe()
2814 mutex_init(&lp->stats_lock); in axienet_probe()
2815 seqcount_mutex_init(&lp->hw_stats_seqcount, &lp->stats_lock); in axienet_probe()
2816 INIT_DEFERRABLE_WORK(&lp->stats_work, axienet_refresh_stats); in axienet_probe()
2818 lp->axi_clk = devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk"); in axienet_probe()
2819 if (!lp->axi_clk) { in axienet_probe()
2823 lp->axi_clk = devm_clk_get_optional(&pdev->dev, NULL); in axienet_probe()
2825 if (IS_ERR(lp->axi_clk)) { in axienet_probe()
2826 ret = PTR_ERR(lp->axi_clk); in axienet_probe()
2829 ret = clk_prepare_enable(lp->axi_clk); in axienet_probe()
2831 dev_err(&pdev->dev, "Unable to enable AXI clock: %d\n", ret); in axienet_probe()
2835 lp->misc_clks[0].id = "axis_clk"; in axienet_probe()
2836 lp->misc_clks[1].id = "ref_clk"; in axienet_probe()
2837 lp->misc_clks[2].id = "mgt_clk"; in axienet_probe()
2839 ret = devm_clk_bulk_get_optional(&pdev->dev, XAE_NUM_MISC_CLOCKS, lp->misc_clks); in axienet_probe()
2843 ret = clk_bulk_prepare_enable(XAE_NUM_MISC_CLOCKS, lp->misc_clks); in axienet_probe()
2848 lp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ðres); in axienet_probe()
2849 if (IS_ERR(lp->regs)) { in axienet_probe()
2850 ret = PTR_ERR(lp->regs); in axienet_probe()
2853 lp->regs_start = ethres->start; in axienet_probe()
2856 lp->features = 0; in axienet_probe()
2859 lp->features |= XAE_FEATURE_STATS; in axienet_probe()
2861 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value); in axienet_probe()
2865 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM; in axienet_probe()
2867 ndev->features |= NETIF_F_HW_CSUM; in axienet_probe()
2870 lp->features |= XAE_FEATURE_FULL_TX_CSUM; in axienet_probe()
2872 ndev->features |= NETIF_F_IP_CSUM; in axienet_probe()
2876 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value); in axienet_probe()
2880 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM; in axienet_probe()
2881 ndev->features |= NETIF_F_RXCSUM; in axienet_probe()
2884 lp->features |= XAE_FEATURE_FULL_RX_CSUM; in axienet_probe()
2885 ndev->features |= NETIF_F_RXCSUM; in axienet_probe()
2889 /* For supporting jumbo frames, the Axi Ethernet hardware must have in axienet_probe()
2893 * the device-tree and accordingly set flags. in axienet_probe()
2895 of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem); in axienet_probe()
2897 lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node, in axienet_probe()
2898 "xlnx,switch-x-sgmii"); in axienet_probe()
2901 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value); in axienet_probe()
2903 netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode"); in axienet_probe()
2906 lp->phy_mode = PHY_INTERFACE_MODE_MII; in axienet_probe()
2909 lp->phy_mode = PHY_INTERFACE_MODE_GMII; in axienet_probe()
2912 lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID; in axienet_probe()
2915 lp->phy_mode = PHY_INTERFACE_MODE_SGMII; in axienet_probe()
2918 lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX; in axienet_probe()
2921 ret = -EINVAL; in axienet_probe()
2925 ret = of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode); in axienet_probe()
2929 if (lp->switch_x_sgmii && lp->phy_mode != PHY_INTERFACE_MODE_SGMII && in axienet_probe()
2930 lp->phy_mode != PHY_INTERFACE_MODE_1000BASEX) { in axienet_probe()
2931 dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\n"); in axienet_probe()
2932 ret = -EINVAL; in axienet_probe()
2936 if (!of_property_present(pdev->dev.of_node, "dmas")) { in axienet_probe()
2937 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ in axienet_probe()
2938 np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); in axienet_probe()
2945 dev_err(&pdev->dev, in axienet_probe()
2946 "unable to get DMA resource\n"); in axienet_probe()
2950 lp->dma_regs = devm_ioremap_resource(&pdev->dev, in axienet_probe()
2952 lp->rx_irq = irq_of_parse_and_map(np, 1); in axienet_probe()
2953 lp->tx_irq = irq_of_parse_and_map(np, 0); in axienet_probe()
2955 lp->eth_irq = platform_get_irq_optional(pdev, 0); in axienet_probe()
2957 /* Check for these resources directly on the Ethernet node. */ in axienet_probe()
2958 lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); in axienet_probe()
2959 lp->rx_irq = platform_get_irq(pdev, 1); in axienet_probe()
2960 lp->tx_irq = platform_get_irq(pdev, 0); in axienet_probe()
2961 lp->eth_irq = platform_get_irq_optional(pdev, 2); in axienet_probe()
2963 if (IS_ERR(lp->dma_regs)) { in axienet_probe()
2964 dev_err(&pdev->dev, "could not map DMA regs\n"); in axienet_probe()
2965 ret = PTR_ERR(lp->dma_regs); in axienet_probe()
2968 if (lp->rx_irq <= 0 || lp->tx_irq <= 0) { in axienet_probe()
2969 dev_err(&pdev->dev, "could not determine irqs\n"); in axienet_probe()
2970 ret = -ENOMEM; in axienet_probe()
2979 /* Autodetect the need for 64-bit DMA pointers. in axienet_probe()
2988 void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; in axienet_probe()
2994 lp->features |= XAE_FEATURE_DMA_64BIT; in axienet_probe()
2996 dev_info(&pdev->dev, in axienet_probe()
2997 "autodetected 64-bit DMA range\n"); in axienet_probe()
3002 if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { in axienet_probe()
3003 dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit architecture\n"); in axienet_probe()
3004 ret = -EINVAL; in axienet_probe()
3008 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); in axienet_probe()
3010 dev_err(&pdev->dev, "No suitable DMA available\n"); in axienet_probe()
3013 netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); in axienet_probe()
3014 netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); in axienet_probe()
3019 lp->eth_irq = platform_get_irq_optional(pdev, 0); in axienet_probe()
3020 if (lp->eth_irq < 0 && lp->eth_irq != -ENXIO) { in axienet_probe()
3021 ret = lp->eth_irq; in axienet_probe()
3024 tx_chan = dma_request_chan(lp->dev, "tx_chan0"); in axienet_probe()
3027 dev_err_probe(lp->dev, ret, "No Ethernet DMA (TX) channel found\n"); in axienet_probe()
3032 /* As name says VDMA but it has support for DMA channel reset */ in axienet_probe()
3035 dev_err(&pdev->dev, "Reset channel failed\n"); in axienet_probe()
3041 lp->use_dmaengine = 1; in axienet_probe()
3044 if (lp->use_dmaengine) in axienet_probe()
3045 ndev->netdev_ops = &axienet_netdev_dmaengine_ops; in axienet_probe()
3047 ndev->netdev_ops = &axienet_netdev_ops; in axienet_probe()
3048 /* Check for Ethernet core IRQ (optional) */ in axienet_probe()
3049 if (lp->eth_irq <= 0) in axienet_probe()
3050 dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); in axienet_probe()
3053 ret = of_get_mac_address(pdev->dev.of_node, mac_addr); in axienet_probe()
3057 dev_warn(&pdev->dev, "could not find MAC address property: %d\n", in axienet_probe()
3062 spin_lock_init(&lp->rx_cr_lock); in axienet_probe()
3063 spin_lock_init(&lp->tx_cr_lock); in axienet_probe()
3064 INIT_WORK(&lp->rx_dim.work, axienet_rx_dim_work); in axienet_probe()
3065 lp->rx_dim_enabled = true; in axienet_probe()
3066 lp->rx_dim.profile_ix = 1; in axienet_probe()
3067 lp->rx_dma_cr = axienet_calc_cr(lp, axienet_dim_coalesce_count_rx(lp), in axienet_probe()
3069 lp->tx_dma_cr = axienet_calc_cr(lp, XAXIDMA_DFT_TX_THRESHOLD, in axienet_probe()
3074 dev_warn(&pdev->dev, in axienet_probe()
3077 if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII || in axienet_probe()
3078 lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) { in axienet_probe()
3079 np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0); in axienet_probe()
3081 /* Deprecated: Always use "pcs-handle" for pcs_phy. in axienet_probe()
3082 * Falling back to "phy-handle" here is only for in axienet_probe()
3085 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); in axienet_probe()
3088 dev_err(&pdev->dev, "pcs-handle (preferred) or phy-handle required for 1000BaseX/SGMII\n"); in axienet_probe()
3089 ret = -EINVAL; in axienet_probe()
3092 lp->pcs_phy = of_mdio_find_device(np); in axienet_probe()
3093 if (!lp->pcs_phy) { in axienet_probe()
3094 ret = -EPROBE_DEFER; in axienet_probe()
3099 lp->pcs.ops = &axienet_pcs_ops; in axienet_probe()
3100 lp->pcs.poll = true; in axienet_probe()
3103 lp->phylink_config.dev = &ndev->dev; in axienet_probe()
3104 lp->phylink_config.type = PHYLINK_NETDEV; in axienet_probe()
3105 lp->phylink_config.mac_managed_pm = true; in axienet_probe()
3106 lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | in axienet_probe()
3109 __set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces); in axienet_probe()
3110 if (lp->switch_x_sgmii) { in axienet_probe()
3112 lp->phylink_config.supported_interfaces); in axienet_probe()
3114 lp->phylink_config.supported_interfaces); in axienet_probe()
3117 lp->phylink = phylink_create(&lp->phylink_config, pdev->dev.fwnode, in axienet_probe()
3118 lp->phy_mode, in axienet_probe()
3120 if (IS_ERR(lp->phylink)) { in axienet_probe()
3121 ret = PTR_ERR(lp->phylink); in axienet_probe()
3122 dev_err(&pdev->dev, "phylink_create error (%i)\n", ret); in axienet_probe()
3126 ret = register_netdev(lp->ndev); in axienet_probe()
3128 dev_err(lp->dev, "register_netdev() error (%i)\n", ret); in axienet_probe()
3135 phylink_destroy(lp->phylink); in axienet_probe()
3138 if (lp->pcs_phy) in axienet_probe()
3139 put_device(&lp->pcs_phy->dev); in axienet_probe()
3140 if (lp->mii_bus) in axienet_probe()
3143 clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); in axienet_probe()
3144 clk_disable_unprepare(lp->axi_clk); in axienet_probe()
3159 if (lp->phylink) in axienet_remove()
3160 phylink_destroy(lp->phylink); in axienet_remove()
3162 if (lp->pcs_phy) in axienet_remove()
3163 put_device(&lp->pcs_phy->dev); in axienet_remove()
3167 clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); in axienet_remove()
3168 clk_disable_unprepare(lp->axi_clk); in axienet_remove()
3234 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");