Lines Matching +full:in +full:- +full:masks
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
185 /* Bit Masks for Axi Ethernet RAF register */
204 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
206 /* Transmit inter-frame gap adjustment value */
209 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
229 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
233 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
237 /* Bit masks for Axi Ethernet RCW1 register */
240 /* In-Band FCS enable (FCS not stripped) */
249 * stored in register RCW0
253 /* Bit masks for Axi Ethernet TC register */
256 /* In-Band FCS enable (FCS not generated) */
260 /* Inter-frame gap adjustment enable */
263 /* Bit masks for Axi Ethernet FCC register */
267 /* Bit masks for Axi Ethernet EMMC register */
279 /* Bit masks for Axi Ethernet PHYC register */
282 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
291 /* Bit masks for Axi Ethernet ability register */
301 /* Bit masks for Axi Ethernet MDIO interface MC register */
305 /* Bit masks for Axi Ethernet MDIO interface MCR register */
317 /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
320 /* Bit masks for Axi Ethernet UAW1 register */
322 * bits [31:0] are stored in register UAW0
326 /* Bit masks for Axi Ethernet FMC register */
332 /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
340 /* Total number of entries in the hardware multicast table. */
363 /* enum temac_stat - TEMAC statistics counters
419 * struct axidma_bd - Axi Dma buffer descriptor layout
455 * struct skbuf_dma_descriptor - skb for each dma descriptor
460 * @sg_len: number of entries in the sglist.
471 * struct axienet_local - axienet private per device data
478 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
479 * @axi_clk: AXI4-Lite bus clock
480 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
491 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
501 * @tx_bd_ci: Stores the next Tx buffer descriptor in the ring that may be
503 * @tx_bd_tail: Stores the index of the next Tx buffer descriptor in the ring
510 * @hw_last_counter: Last-seen value of each statistic counter
524 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
528 * Txed/Rxed in the existing hardware. If jumbo option is
626 * struct axienet_option - Used to set axi ethernet hardware options
629 * @m_or: Mask to be ORed for setting the option in the register
638 * axienet_ior - Memory mapped Axi Ethernet register read
648 return ioread32(lp->regs + offset); in axienet_ior()
658 if (lp->mii_bus) in axienet_lock_mii()
659 mutex_lock(&lp->mii_bus->mdio_lock); in axienet_lock_mii()
664 if (lp->mii_bus) in axienet_unlock_mii()
665 mutex_unlock(&lp->mii_bus->mdio_lock); in axienet_unlock_mii()
669 * axienet_iow - Memory mapped Axi Ethernet register write
680 iowrite32(value, lp->regs + offset); in axienet_iow()
684 * axienet_dma_out32 - Memory mapped Axi DMA register write.
696 iowrite32(value, lp->dma_regs + reg); in axienet_dma_out32()
701 * axienet_dma_out64 - Memory mapped Axi DMA register write.
712 iowrite64(value, lp->dma_regs + reg); in axienet_dma_out64()
718 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_out_addr()
734 /* Function prototypes visible in xilinx_axienet_mdio.c for other files */