Lines Matching +full:100 +full:base +full:- +full:tx
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
35 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
38 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
109 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
110 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
124 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
129 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
130 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
147 #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
152 #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
162 #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
181 #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
190 #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
192 #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
199 #define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
201 #define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
205 #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
206 /* Transmit inter-frame gap adjustment value */
219 #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
240 /* In-Band FCS enable (FCS not stripped) */
256 /* In-Band FCS enable (FCS not generated) */
260 /* Inter-frame gap adjustment enable */
265 #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
273 #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
276 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
282 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
285 #define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */
288 #define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */
363 /* enum temac_stat - TEMAC statistics counters
419 * struct axidma_bd - Axi Dma buffer descriptor layout
445 u32 app1; /* TX start << 16 | insert */
446 u32 app2; /* TX csum seed */
455 * struct skbuf_dma_descriptor - skb for each dma descriptor
471 * struct axienet_local - axienet private per device data
479 * @axi_clk: AXI4-Lite bus clock
480 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
484 * @regs: Base address for the axienet_local device address space
485 * @dma_regs: Base address for the axidma device address space
501 * @napi_tx: NAPI TX control structure
503 * @tx_dma_cr: Nominal content of TX DMA control register
504 * @tx_dma_started: Set when TX DMA is started
505 * @tx_bd_v: Virtual address of the TX buffer descriptor ring
506 * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring
507 * @tx_bd_num: Size of TX buffer descriptor ring
508 * @tx_bd_ci: Stores the next Tx buffer descriptor in the ring that may be
509 * complete. Only updated at runtime by TX NAPI poll.
510 * @tx_bd_tail: Stores the index of the next Tx buffer descriptor in the ring
512 * @tx_packets: TX packet count for statistics
513 * @tx_bytes: TX byte count for statistics
514 * @tx_stat_sync: Synchronization object for TX stats
515 * @hw_stat_base: Base offset for statistics counters. This may be nonzero if
517 * @hw_last_counter: Last-seen value of each statistic counter
528 * @tx_irq: Axidma TX IRQ number
531 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
540 * @tx_chan: TX DMA channel.
542 * @tx_skb_ring: Pointer to TX skb ring buffer array.
544 * @tx_ring_head: TX skb ring buffer head index.
545 * @tx_ring_tail: TX skb ring buffer tail index.
632 * struct axienet_option - Used to set axi ethernet hardware options
644 * axienet_ior - Memory mapped Axi Ethernet register read
646 * @offset: Address offset from the base address of Axi Ethernet core
654 return ioread32(lp->regs + offset); in axienet_ior()
664 if (lp->mii_bus) in axienet_lock_mii()
665 mutex_lock(&lp->mii_bus->mdio_lock); in axienet_lock_mii()
670 if (lp->mii_bus) in axienet_unlock_mii()
671 mutex_unlock(&lp->mii_bus->mdio_lock); in axienet_unlock_mii()
675 * axienet_iow - Memory mapped Axi Ethernet register write
677 * @offset: Address offset from the base address of Axi Ethernet core
686 iowrite32(value, lp->regs + offset); in axienet_iow()
690 * axienet_dma_out32 - Memory mapped Axi DMA register write.
692 * @reg: Address offset from the base address of the Axi DMA core
702 iowrite32(value, lp->dma_regs + reg); in axienet_dma_out32()
707 * axienet_dma_out64 - Memory mapped Axi DMA register write.
709 * @reg: Address offset from the base address of the Axi DMA core
718 iowrite64(value, lp->dma_regs + reg); in axienet_dma_out64()
724 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_out_addr()