Lines Matching +full:multi +full:- +full:gmac
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * File: via-velocity.h
10 * Author: Chuang Liang-Shing, AJ Jiang
21 #define VELOCITY_NAME "via-velocity"
30 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
126 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
167 __le16 len; /* bits 0--13; bit 15 - owner */
185 __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */
194 __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */
200 u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
210 __le16 size; /* bits 0--13 - size, bit 15 - queue */
429 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
430 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
431 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
459 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
460 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
461 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
942 when (1) NoBuf -> RxThreshold = SF
943 (2) OK -> RxThreshold = original value
1140 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1141 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1143 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1144 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1147 #define mac_read_isr(regs) readl(&((regs)->ISR))
1148 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1149 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1151 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1152 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1153 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1156 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1160 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1164 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1168 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1172 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1176 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1182 BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR)); in mac_eeprom_reload()
1187 } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR))); in mac_eeprom_reload()
1378 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)]))
1380 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1449 * velocity_get_ip - find an IP address for the device
1454 * addresses on this chain then we use the first - multi-IP WOL is not
1463 int res = -ENOENT; in velocity_get_ip()
1466 in_dev = __in_dev_get_rcu(vptr->netdev); in velocity_get_ip()
1468 ifa = rcu_dereference(in_dev->ifa_list); in velocity_get_ip()
1470 memcpy(vptr->ip_addr, &ifa->ifa_address, 4); in velocity_get_ip()
1479 * velocity_update_hw_mibs - fetch MIB counters from chip
1493 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)); in velocity_update_hw_mibs()
1495 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR))); in velocity_update_hw_mibs()
1497 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR)); in velocity_update_hw_mibs()
1499 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL; in velocity_update_hw_mibs()
1500 vptr->mib_counter[i] += tmp; in velocity_update_hw_mibs()
1505 * init_flow_control_register - set up flow control
1513 struct mac_regs __iomem * regs = vptr->mac_regs; in init_flow_control_register()
1517 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set); in init_flow_control_register()
1518 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr); in init_flow_control_register()
1521 writew(0xFFFF, ®s->tx_pause_timer); in init_flow_control_register()
1524 writew(vptr->options.numrx, ®s->RBRDU); in init_flow_control_register()