Lines Matching +full:half +full:- +full:duplex

1 /* SPDX-License-Identifier: GPL-2.0 */
4  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
30  *   - used by firmware to store packets to be forwarded to other port
31  *   - 8 total pools per slice
32  *   - only used in switch mode (as no forwarding in mac mode)
38  *   - used by firmware to store packets received from host core
39  *   - 16 total pools per slice
40  *   - 8 pools per port per slice and each slice handles both ports
41  *   - only 4 out of 8 pools used per port (as only 4 real QoS levels in ICSSG)
42  *   - switch mode: 8 total pools used
43  *   - mac mode:    4 total pools used
54 /* Defines for host egress path - express and preemptible buffers
55  *   - used by firmware to store express and preemptible packets
57  *   - used by both mac/switch modes
60 #define PRUETH_SW_HOST_PRE_BUF_POOL_SIZE	(SZ_16K - SZ_2K)
95 #define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1)
174 /* SR1.0-specific bits */
210  *	- ss: sequence number. Currently not used by driver.
214 /* SR1.0 pstate speed/duplex command to set speed and duplex settings
217  *	- ss: sequence number. Currently not used by driver.
218  *	- P: port number (for switch mode).
219  *	- N: Speed/Duplex state:
220  *		0x0 - 10Mbps/Half duplex;
221  *		0x8 - 10Mbps/Full duplex;
222  *		0x2 - 100Mbps/Half duplex;
223  *		0xa - 100Mbps/Full duplex;
224  *		0xc - 1Gbps/Full duplex;
305  * struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM
308  * @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID)
316  * struct prueth_fdb_slot - Result of FDB slot lookup