Lines Matching +full:0 +full:xfffb0000

21 #define PRUETH_PKT_TYPE_CMD	0x10
27 #define PRUETH_RX_FLOW_DATA	0
54 #define ICSSG_FW_MGMT_CMD_HEADER	0x81
55 #define ICSSG_FW_MGMT_FDB_CMD_TYPE	0x03
56 #define ICSSG_FW_MGMT_CMD_TYPE		0x04
57 #define ICSSG_FW_MGMT_PKT		0x80000000
64 	ICSSG_EMAC_PORT_DISABLE = 0,
88 #define EMAC_NONE           0xffff0000
89 #define EMAC_PRU0_P_DI      0xffff0004
90 #define EMAC_PRU1_P_DI      0xffff0040
91 #define EMAC_TX_P_DI        0xffff0100
93 #define EMAC_PRU0_P_EN      0xfffb0000
94 #define EMAC_PRU1_P_EN      0xffbf0000
95 #define EMAC_TX_P_EN        0xfeff0000
97 #define EMAC_P_BLOCK        0xffff0040
98 #define EMAC_TX_P_BLOCK     0xffff0200
99 #define EMAC_P_UNBLOCK      0xffbf0000
100 #define EMAC_TX_P_UNBLOCK   0xfdff0000
101 #define EMAC_LEAN_EN        0xfff70000
102 #define EMAC_LEAN_DI        0xffff0008
104 #define EMAC_ACCEPT_ALL     0xffff0001
105 #define EMAC_ACCEPT_TAG     0xfffe0002
106 #define EMAC_ACCEPT_PRIOR   0xfffc0000
109 #define ICSSG_CONFIG_OFFSET	0x0
112 #define ICSSG_CONFIG_OFFSET_SLICE0   0
113 #define ICSSG_CONFIG_OFFSET_SLICE1   0x8000
121 #define ICSSG_FLAG_MASK		0xff00ffff
123 /* SR1.0-specific bits */
128 #define PRUETH_RX_MGM_FLOW_RESPONSE_SR1		0
138 #define MSMC_RAM_SIZE_SR1	(SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */
143 	__le32 addr_hi;		/* MSMC Buffer pool base address high. Must be 0 */
157 /* SR1.0 shutdown command to stop processing at firmware.
158  * Command format: 0x8101ss00, where
161 #define ICSSG_SHUTDOWN_CMD_SR1		0x81010000
163 /* SR1.0 pstate speed/duplex command to set speed and duplex settings
165  * Command format: 0x8102ssPN, where
169  *		0x0 - 10Mbps/Half duplex;
170  *		0x8 - 10Mbps/Full duplex;
171  *		0x2 - 100Mbps/Half duplex;
172  *		0xa - 100Mbps/Full duplex;
173  *		0xc - 1Gbps/Full duplex;
174  *		NOTE: The above are the same value as bits [3..1](slice 0)
177 #define ICSSG_PSTATE_SPEED_DUPLEX_CMD_SR1	0x81020000
235 #define ICSSG_FDB_ENTRY_P0_MEMBERSHIP         BIT(0)
277 	ICSSG_IETFPE_STATE_UNKNOWN = 0,