Lines Matching +full:pruss +full:- +full:mii
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
79 * struct map - ICSSG Queue Map
112 struct prueth *prueth = emac->prueth; in icssg_config_mii_init_fw_offload()
113 int mii = prueth_emac_slice(emac); in icssg_config_mii_init_fw_offload() local
117 mii_rt = prueth->mii_rt; in icssg_config_mii_init_fw_offload()
119 txcfg_reg = (mii == ICSS_MII0) ? PRUSS_MII_RT_TXCFG0 : in icssg_config_mii_init_fw_offload()
121 pcnt_reg = (mii == ICSS_MII0) ? PRUSS_MII_RT_RX_PCNT0 : in icssg_config_mii_init_fw_offload()
128 if (emac->phy_if == PHY_INTERFACE_MODE_MII && mii == ICSS_MII1) in icssg_config_mii_init_fw_offload()
130 else if (emac->phy_if != PHY_INTERFACE_MODE_MII && mii == ICSS_MII0) in icssg_config_mii_init_fw_offload()
139 struct prueth *prueth = emac->prueth; in icssg_config_mii_init()
144 mii_rt = prueth->mii_rt; in icssg_config_mii_init()
153 /* In MII mode TX lines swapped inside ICSSG, so TX_MUX_SEL cfg need in icssg_config_mii_init()
156 if (emac->phy_if == PHY_INTERFACE_MODE_MII && slice == ICSS_MII0) in icssg_config_mii_init()
158 else if (emac->phy_if != PHY_INTERFACE_MODE_MII && slice == ICSS_MII1) in icssg_config_mii_init()
167 struct regmap *miig_rt = prueth->miig_rt; in icssg_miig_queues_init()
168 void __iomem *smem = prueth->shram.va; in icssg_miig_queues_init()
200 if (mp->special) { in icssg_miig_queues_init()
212 pdword[0] |= mp->flags; in icssg_miig_queues_init()
213 pdaddr = mp->pd_addr_start + i * pd_size; in icssg_miig_queues_init()
216 queue = mp->queue; in icssg_miig_queues_init()
225 struct prueth *prueth = emac->prueth; in icssg_config_ipg()
229 switch (emac->speed) { in icssg_config_ipg()
231 ipg = emac->is_sr1 ? MII_RT_TX_IPG_1G_SR1 : MII_RT_TX_IPG_1G; in icssg_config_ipg()
234 ipg = emac->is_sr1 ? MII_RT_TX_IPG_100M_SR1 : MII_RT_TX_IPG_100M; in icssg_config_ipg()
238 if (emac->is_sr1) in icssg_config_ipg()
245 netdev_err(emac->ndev, "Unsupported link speed\n"); in icssg_config_ipg()
249 icssg_mii_update_ipg(prueth->mii_rt, slice, ipg); in icssg_config_ipg()
258 p = emac->dram.va + MGR_R30_CMD_OFFSET; in emac_r30_cmd_init()
261 writel(EMAC_NONE, &p->cmd[i]); in emac_r30_cmd_init()
270 p = emac->dram.va + MGR_R30_CMD_OFFSET; in emac_r30_is_done()
273 cmd = readl(&p->cmd[i]); in emac_r30_is_done()
285 struct prueth *prueth = emac->prueth; in prueth_fw_offload_buffer_setup()
290 addr = lower_32_bits(prueth->msmcram.pa); in prueth_fw_offload_buffer_setup()
295 dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n"); in prueth_fw_offload_buffer_setup()
296 return -EINVAL; in prueth_fw_offload_buffer_setup()
299 bpool_cfg = emac->dram.va + BUFFER_POOL_0_ADDR_OFFSET; in prueth_fw_offload_buffer_setup()
331 rxq_ctx = emac->dram.va + HOST_RX_Q_PRE_CONTEXT_OFFSET; in prueth_fw_offload_buffer_setup()
333 writel(addr, &rxq_ctx->start[i]); in prueth_fw_offload_buffer_setup()
336 writel(addr - SZ_2K, &rxq_ctx->end); in prueth_fw_offload_buffer_setup()
345 struct prueth *prueth = emac->prueth; in prueth_emac_buffer_setup()
354 addr = lower_32_bits(prueth->msmcram.pa); in prueth_emac_buffer_setup()
359 dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n"); in prueth_emac_buffer_setup()
360 return -EINVAL; in prueth_emac_buffer_setup()
363 bpool_cfg = emac->dram.va + BUFFER_POOL_0_ADDR_OFFSET; in prueth_emac_buffer_setup()
381 /* Pre-emptible RX buffer queue */ in prueth_emac_buffer_setup()
382 rxq_ctx = emac->dram.va + HOST_RX_Q_PRE_CONTEXT_OFFSET; in prueth_emac_buffer_setup()
384 writel(addr, &rxq_ctx->start[i]); in prueth_emac_buffer_setup()
387 writel(addr, &rxq_ctx->end); in prueth_emac_buffer_setup()
390 rxq_ctx = emac->dram.va + HOST_RX_Q_EXP_CONTEXT_OFFSET; in prueth_emac_buffer_setup()
392 writel(addr, &rxq_ctx->start[i]); in prueth_emac_buffer_setup()
395 writel(addr, &rxq_ctx->end); in prueth_emac_buffer_setup()
405 u32 addr = prueth->shram.pa + EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET; in icssg_init_emac_mode()
409 if (prueth->emacs_initialized) in icssg_init_emac_mode()
413 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, in icssg_init_emac_mode()
416 regmap_write(prueth->miig_rt, FDB_GEN_CFG2, (FDB_PRU0_EN | FDB_PRU1_EN | FDB_HOST_EN)); in icssg_init_emac_mode()
417 prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va + in icssg_init_emac_mode()
419 for (i = 0; i < SZ_4K - 1; i++) { in icssg_init_emac_mode()
420 prueth->vlan_tbl[i].fid = i; in icssg_init_emac_mode()
421 prueth->vlan_tbl[i].fid_c1 = 0; in icssg_init_emac_mode()
424 icssg_class_set_host_mac_addr(prueth->miig_rt, mac); in icssg_init_emac_mode()
429 u32 addr = prueth->shram.pa + EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET; in icssg_init_fw_offload_mode()
432 if (prueth->emacs_initialized) in icssg_init_fw_offload_mode()
436 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, in icssg_init_fw_offload_mode()
439 regmap_write(prueth->miig_rt, FDB_GEN_CFG2, FDB_EN_ALL); in icssg_init_fw_offload_mode()
440 prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va + in icssg_init_fw_offload_mode()
442 for (i = 0; i < SZ_4K - 1; i++) { in icssg_init_fw_offload_mode()
443 prueth->vlan_tbl[i].fid = i; in icssg_init_fw_offload_mode()
444 prueth->vlan_tbl[i].fid_c1 = 0; in icssg_init_fw_offload_mode()
447 if (prueth->hw_bridge_dev) in icssg_init_fw_offload_mode()
448 icssg_class_set_host_mac_addr(prueth->miig_rt, prueth->hw_bridge_dev->dev_addr); in icssg_init_fw_offload_mode()
449 icssg_set_pvid(prueth, prueth->default_vlan, PRUETH_PORT_HOST); in icssg_init_fw_offload_mode()
454 void __iomem *config = emac->dram.va + ICSSG_CONFIG_OFFSET; in icssg_config()
458 if (prueth->is_switch_mode || prueth->is_hsr_offload_mode) in icssg_config()
466 emac->speed = SPEED_1000; in icssg_config()
467 emac->duplex = DUPLEX_FULL; in icssg_config()
468 if (!phy_interface_mode_is_rgmii(emac->phy_if)) { in icssg_config()
469 emac->speed = SPEED_100; in icssg_config()
470 emac->duplex = DUPLEX_FULL; in icssg_config()
472 regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET, in icssg_config()
474 icssg_miig_set_interface_mode(prueth->miig_rt, slice, emac->phy_if); in icssg_config()
475 if (prueth->is_switch_mode || prueth->is_hsr_offload_mode) in icssg_config()
480 icssg_update_rgmii_cfg(prueth->miig_rt, emac); in icssg_config()
483 pruss_cfg_gpimode(prueth->pruss, prueth->pru_id[slice], in icssg_config()
487 pruss_cfg_xfr_enable(prueth->pruss, PRU_TYPE_PRU, true); in icssg_config()
488 pruss_cfg_xfr_enable(prueth->pruss, PRU_TYPE_RTU, true); in icssg_config()
491 pru_rproc_set_ctable(prueth->pru[slice], PRU_C28, 0x100 << 8); in icssg_config()
492 pru_rproc_set_ctable(prueth->rtu[slice], PRU_C28, 0x100 << 8); in icssg_config()
493 pru_rproc_set_ctable(prueth->txpru[slice], PRU_C28, 0x100 << 8); in icssg_config()
496 writew(emac->rx_flow_id_base, &flow_cfg->rx_base_flow); in icssg_config()
497 writew(0, &flow_cfg->mgm_base_flow); in icssg_config()
501 if (prueth->is_switch_mode || prueth->is_hsr_offload_mode) in icssg_config()
543 int ret = -ETIMEDOUT; in icssg_set_port_state()
547 p = emac->dram.va + MGR_R30_CMD_OFFSET; in icssg_set_port_state()
550 netdev_err(emac->ndev, "invalid port command\n"); in icssg_set_port_state()
551 return -EINVAL; in icssg_set_port_state()
555 mutex_lock(&emac->cmd_lock); in icssg_set_port_state()
558 writel(emac_r32_bitmask[cmd].cmd[i], &p->cmd[i]); in icssg_set_port_state()
564 if (ret == -ETIMEDOUT) in icssg_set_port_state()
565 netdev_err(emac->ndev, "timeout waiting for command done\n"); in icssg_set_port_state()
567 mutex_unlock(&emac->cmd_lock); in icssg_set_port_state()
577 if (!emac->half_duplex) in icssg_config_half_duplex()
581 writel(val, emac->dram.va + HD_RAND_SEED_OFFSET); in icssg_config_half_duplex()
589 switch (emac->speed) { in icssg_config_set_speed()
601 netdev_err(emac->ndev, "Unsupported link speed\n"); in icssg_config_set_speed()
605 if (emac->duplex == DUPLEX_HALF) in icssg_config_set_speed()
608 writeb(fw_speed, emac->dram.va + PORT_LINK_SPEED_OFFSET); in icssg_config_set_speed()
615 struct prueth *prueth = emac->prueth; in icssg_send_fdb_msg()
627 memcpy_toio(prueth->shram.va + addr + 4, cmd, sizeof(*cmd)); in icssg_send_fdb_msg()
634 netdev_err(emac->ndev, "Timedout sending HWQ message\n"); in icssg_send_fdb_msg()
638 memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp)); in icssg_send_fdb_msg()
656 /* 1-1 VID-FID mapping is already setup */ in icssg_fdb_setup()
662 fdb_cmd->header = ICSSG_FW_MGMT_CMD_HEADER; in icssg_fdb_setup()
663 fdb_cmd->type = ICSSG_FW_MGMT_FDB_CMD_TYPE; in icssg_fdb_setup()
664 fdb_cmd->seqnum = ++(emac->prueth->icssg_hwcmdseq); in icssg_fdb_setup()
665 fdb_cmd->param = cmd; in icssg_fdb_setup()
666 fdb_cmd->param |= (slice << 4); in icssg_fdb_setup()
668 memcpy(&fdb_cmd->cmd_args[0], addr, 4); in icssg_fdb_setup()
669 memcpy(&fdb_cmd->cmd_args[1], &addr[4], 2); in icssg_fdb_setup()
670 fdb_cmd->cmd_args[2] = fdb_slot; in icssg_fdb_setup()
672 netdev_dbg(emac->ndev, "MAC %pM slot %X FID %X\n", addr, fdb_slot, fid); in icssg_fdb_setup()
696 return -EINVAL; in icssg_fdb_add_del()
719 slot = (struct prueth_fdb_slot __force *)(emac->dram.va + FDB_CMD_BUFFER); in icssg_fdb_lookup()
721 if (ether_addr_equal(addr, slot->mac) && vid == slot->fid) in icssg_fdb_lookup()
722 return (slot->fid_c2 & ~ICSSG_FDB_ENTRY_VALID); in icssg_fdb_lookup()
733 struct prueth *prueth = emac->prueth; in icssg_vtbl_modify()
737 tbl = prueth->vlan_tbl; in icssg_vtbl_modify()
738 spin_lock(&prueth->vtbl_lock); in icssg_vtbl_modify()
754 spin_unlock(&prueth->vtbl_lock); in icssg_vtbl_modify()
760 struct prueth *prueth = emac->prueth; in icssg_get_pvid()
763 if (emac->port_id == PRUETH_PORT_MII0) in icssg_get_pvid()
764 pvid = readl(prueth->shram.va + EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET); in icssg_get_pvid()
766 pvid = readl(prueth->shram.va + EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET); in icssg_get_pvid()
782 writel(pvid, prueth->shram.va + EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET); in icssg_set_pvid()
784 writel(pvid, prueth->shram.va + EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET); in icssg_set_pvid()
786 writel(pvid, prueth->shram.va + EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET); in icssg_set_pvid()