21 #define MII_RT_TX_IPG_100M	0x17
22 #define MII_RT_TX_IPG_1G	0xb
23 #define MII_RT_TX_IPG_100M_SR1	0x166
24 #define MII_RT_TX_IPG_1G_SR1	0x1a
27 #define	ICSSG_QUEUE_OFFSET		0xd00
28 #define	ICSSG_QUEUE_PEEK_OFFSET		0xe00
29 #define	ICSSG_QUEUE_CNT_OFFSET		0xe40
30 #define	ICSSG_QUEUE_RESET_OFFSET	0xf40
66 #define FDB_GEN_CFG1		0x60
73 #define FDB_GEN_CFG2		0x64
77 #define FDB_PRU0_EN		BIT(0)
98 		{ PORT_HI_Q_SLICE0, PORT_DESC0_HI, 0x200000, 0 },
99 		{ PORT_LO_Q_SLICE0, PORT_DESC0_LO, 0, 0 },
100 		{ HOST_HI_Q_SLICE0, HOST_DESC0_HI, 0x200000, 0 },
101 		{ HOST_LO_Q_SLICE0, HOST_DESC0_LO, 0, 0 },
102 		{ HOST_SPL_Q_SLICE0, HOST_SPPD0, 0x400000, 1 },
105 		{ PORT_HI_Q_SLICE1, PORT_DESC1_HI, 0xa00000, 0 },
106 		{ PORT_LO_Q_SLICE1, PORT_DESC1_LO, 0x800000, 0 },
107 		{ HOST_HI_Q_SLICE1, HOST_DESC1_HI, 0xa00000, 0 },
108 		{ HOST_LO_Q_SLICE1, HOST_DESC1_LO, 0x800000, 0 },
109 		{ HOST_SPL_Q_SLICE1, HOST_SPPD1, 0xc00000, 1 },
137 	regmap_write(mii_rt, pcnt_reg, 0x1);  in icssg_config_mii_init_fw_offload()
165 	regmap_write(mii_rt, pcnt_reg, 0x1);  in icssg_config_mii_init()
173 	int queue = 0, i, j;  in icssg_miig_queues_init()
180 	for (i = 0; i < ICSSG_NUM_TX_QUEUES; i++) {  in icssg_miig_queues_init()
188 	for (i = 0; i < ICSSG_NUM_OTHER_QUEUES; i++) {  in icssg_miig_queues_init()
197 	for (j = 0; j < ICSSG_NUM_OTHER_QUEUES; j++) {  in icssg_miig_queues_init()
211 		for (i = 0; i < num_pds; i++) {  in icssg_miig_queues_init()
212 			memset(pd, 0, pd_size);  in icssg_miig_queues_init()
214 			pdword[0] &= ICSSG_FLAG_MASK;  in icssg_miig_queues_init()
215 			pdword[0] |= mp->flags;  in icssg_miig_queues_init()
240 		/* Firmware hardcodes IPG for SR1.0 */  in icssg_config_ipg()
263 	for (i = 0; i < 4; i++)  in emac_r30_cmd_init()
275 	for (i = 0; i < 4; i++) {  in emac_r30_is_done()
278 			return 0;  in emac_r30_is_done()
312 	for (i = 0; i <  PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE; i++) {  in prueth_fw_offload_buffer_setup()
322 	for (i = 0; i < PRUETH_NUM_LI_BUF_POOLS_PER_SLICE; i++) {  in prueth_fw_offload_buffer_setup()
335 			writel(0, &bpool_cfg[cfg_idx].addr);  in prueth_fw_offload_buffer_setup()
336 			writel(0, &bpool_cfg[cfg_idx].len);  in prueth_fw_offload_buffer_setup()
345 	for (i = 0; i < 3; i++)  in prueth_fw_offload_buffer_setup()
356 	for (i = 0; i < 3; i++)  in prueth_fw_offload_buffer_setup()
366 	writel(addr, &rxq_ctx->start[0]);  in prueth_fw_offload_buffer_setup()
368 	return 0;  in prueth_fw_offload_buffer_setup()
396 	 *  - in mac mode - no forwarding so initialize all pools to 0  in prueth_emac_buffer_setup()
399 	for (i = 0; i <  PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE; i++) {  in prueth_emac_buffer_setup()
400 		writel(0, &bpool_cfg[i].addr);  in prueth_emac_buffer_setup()
401 		writel(0, &bpool_cfg[i].len);  in prueth_emac_buffer_setup()
409 	for (i = 0; i < PRUETH_NUM_LI_BUF_POOLS_PER_SLICE; i++) {  in prueth_emac_buffer_setup()
421 			writel(0, &bpool_cfg[cfg_idx].addr);  in prueth_emac_buffer_setup()
422 			writel(0, &bpool_cfg[cfg_idx].len);  in prueth_emac_buffer_setup()
431 	for (i = 0; i < 3; i++)  in prueth_emac_buffer_setup()
442 	for (i = 0; i < 3; i++)  in prueth_emac_buffer_setup()
452 	writel(addr, &rxq_ctx->start[0]);  in prueth_emac_buffer_setup()
454 	return 0;  in prueth_emac_buffer_setup()
460 	 * back to the emac mode, the host mac address has to be set as 0.  in icssg_init_emac_mode()
464 	u8 mac[ETH_ALEN] = { 0 };  in icssg_init_emac_mode()
475 	for (i = 0; i < SZ_4K - 1; i++) {  in icssg_init_emac_mode()
477 		prueth->vlan_tbl[i].fid_c1 = 0;  in icssg_init_emac_mode()
498 	for (i = 0; i < SZ_4K - 1; i++) {  in icssg_init_fw_offload_mode()
500 		prueth->vlan_tbl[i].fid_c1 = 0;  in icssg_init_fw_offload_mode()
515 	memset_io(config, 0, TAS_GATE_MASK_LIST0);  in icssg_config()
542 	/* set C28 to 0x100 */  in icssg_config()
543 	pru_rproc_set_ctable(prueth->pru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
544 	pru_rproc_set_ctable(prueth->rtu[slice], PRU_C28, 0x100 << 8);  in icssg_config()
545 	pru_rproc_set_ctable(prueth->txpru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
549 	writew(0, &flow_cfg->mgm_base_flow);  in icssg_config()
550 	writeb(0, config + SPL_PKT_DEFAULT_PRIORITY);  in icssg_config()
551 	writeb(0, config + QUEUE_NUM_UNTAGGED);  in icssg_config()
562 	return 0;  in icssg_config()
568 	{{0xffff0004, 0xffff0100, 0xffff0004, EMAC_NONE}},	/* EMAC_PORT_DISABLE */
569 	{{0xfffb0040, 0xfeff0200, 0xfeff0200, EMAC_NONE}},	/* EMAC_PORT_BLOCK */
570 	{{0xffbb0000, 0xfcff0000, 0xdcfb0000, EMAC_NONE}},	/* EMAC_PORT_FORWARD */
571 	{{0xffbb0000, 0xfcff0000, 0xfcff2000, EMAC_NONE}},	/* EMAC_PORT_FORWARD_WO_LEARNING */
572 	{{0xffff0001, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT ALL */
573 	{{0xfffe0002, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT TAGGED */
574 	{{0xfffc0000, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT UNTAGGED and PRIO */
575 	{{EMAC_NONE,  0xffff0020, EMAC_NONE, EMAC_NONE}},	/* TAS Trigger List change */
576 	{{EMAC_NONE,  0xdfff1000, EMAC_NONE, EMAC_NONE}},	/* TAS set state ENABLE*/
577 	{{EMAC_NONE,  0xefff2000, EMAC_NONE, EMAC_NONE}},	/* TAS set state RESET*/
578 	{{EMAC_NONE,  0xcfff0000, EMAC_NONE, EMAC_NONE}},	/* TAS set state DISABLE*/
579 	{{EMAC_NONE,  EMAC_NONE,  0xffff0400, EMAC_NONE}},	/* UC flooding ENABLE*/
580 	{{EMAC_NONE,  EMAC_NONE,  0xfbff0000, EMAC_NONE}},	/* UC flooding DISABLE*/
581 	{{EMAC_NONE,  EMAC_NONE,  0xffff0800, EMAC_NONE}},	/* MC flooding ENABLE*/
582 	{{EMAC_NONE,  EMAC_NONE,  0xf7ff0000, EMAC_NONE}},	/* MC flooding DISABLE*/
583 	{{EMAC_NONE,  0xffff4000, EMAC_NONE, EMAC_NONE}},	/* Preemption on Tx ENABLE*/
584 	{{EMAC_NONE,  0xbfff0000, EMAC_NONE, EMAC_NONE}},	/* Preemption on Tx DISABLE*/
585 	{{0xffff0010,  EMAC_NONE, 0xffff0010, EMAC_NONE}},	/* VLAN AWARE*/
586 	{{0xffef0000,  EMAC_NONE, 0xffef0000, EMAC_NONE}},	/* VLAN UNWARE*/
587 	{{0xffff2000, EMAC_NONE, EMAC_NONE, EMAC_NONE}},	/* HSR_RX_OFFLOAD_ENABLE */
588 	{{0xdfff0000, EMAC_NONE, EMAC_NONE, EMAC_NONE}}		/* HSR_RX_OFFLOAD_DISABLE */
596 	int done = 0;  in icssg_set_port_state()
609 	for (i = 0; i < 4; i++)  in icssg_set_port_state()
671 	addr = icssg_queue_pop(prueth, slice == 0 ?  in icssg_send_fdb_msg()
673 	if (addr < 0)  in icssg_send_fdb_msg()
680 	icssg_queue_push(prueth, slice == 0 ?  in icssg_send_fdb_msg()
682 	ret = read_poll_timeout(icssg_queue_pop, addr, addr >= 0,  in icssg_send_fdb_msg()
683 				2000, 20000000, false, prueth, slice == 0 ?  in icssg_send_fdb_msg()
692 	icssg_queue_push(prueth, slice == 0 ?  in icssg_send_fdb_msg()
695 	return 0;  in icssg_send_fdb_msg()
710 	mac_fid[ETH_ALEN + 1] = 0;  in icssg_fdb_setup()
712 	fdb_slot = bitrev32(crc32_le(0, mac_fid, 8)) & PRUETH_SWITCH_FDB_MASK;  in icssg_fdb_setup()
720 	memcpy(&fdb_cmd->cmd_args[0], addr, 4);  in icssg_fdb_setup()
730 	struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };  in icssg_fdb_add_del()
731 	struct mgmt_cmd fdb_cmd = { 0 };  in icssg_fdb_add_del()
746 		return 0;  in icssg_fdb_add_del()
755 	struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };  in icssg_fdb_lookup()
756 	struct mgmt_cmd fdb_cmd = { 0 };  in icssg_fdb_lookup()
772 	for (i = 0; i < 4; i++) {  in icssg_fdb_lookup()
778 	return 0;  in icssg_fdb_lookup()
831 	pvid = (u32 __force)cpu_to_be32((ETH_P_8021Q << 16) | (vid & 0xff));  in icssg_set_pvid()
844 	struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };  in emac_fdb_flow_id_updated()
846 	struct mgmt_cmd fdb_cmd = { 0 };  in emac_fdb_flow_id_updated()
852 	fdb_cmd.param  = 0;  in emac_fdb_flow_id_updated()
855 	fdb_cmd.cmd_args[0] = 0;  in emac_fdb_flow_id_updated()
862 	return fdb_cmd_rsp.status == 1 ? 0 : -EINVAL;  in emac_fdb_flow_id_updated()