Lines Matching +full:tx +full:- +full:rx
1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
45 /* The following registers are for per-qe channel information/status. */
48 #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
49 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
50 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
51 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
54 #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
55 #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
56 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
57 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
59 #define CREG_PIPG 0x34UL /* Inter-Frame Gap */
69 #define CREG_STAT_LCOLL 0x02000000 /* Late TX Collision */
74 #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */
75 #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
79 #define CREG_STAT_RCCOFLOW 0x00001000 /* RX Coll-counter Overflow */
82 #define CREG_STAT_RXFOFLOW 0x00000200 /* RX FIFO Overflow */
83 #define CREG_STAT_RLCOLL 0x00000100 /* RX Late Collision */
85 #define CREG_STAT_CECOFLOW 0x00000040 /* CRC Error-counter Overflow*/
87 #define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */
104 #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
105 #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
106 #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
107 #define CREG_QMASK_RXDROP 0x00000010 /* RX drop */
108 #define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */
109 #define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */
110 #define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */
111 #define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */
121 #define CREG_MMASK_RXCOLL 0x00000400 /* RX Coll-Cntr overflow */
129 /* Per-channel AMD 79C940 MACE registers. */
146 #define MREGS_CHIPID1 0x10UL /* Chip-ID, low bits */
147 #define MREGS_CHIPID2 0x11UL /* Chip-ID, high bits */
157 #define MREGS_RCCNT 0x1bUL /* RX Collision Count */
165 #define MREGS_TXFCNTL_DFCS 0x08 /* Disable TX FCS */
166 #define MREGS_TXFCNTL_AUTOPAD 0x01 /* TX auto pad */
168 #define MREGS_TXFSTAT_VALID 0x80 /* TX valid */
169 #define MREGS_TXFSTAT_UNDERFLOW 0x40 /* TX underflow */
170 #define MREGS_TXFSTAT_LCOLL 0x20 /* TX late collision */
171 #define MREGS_TXFSTAT_MRETRY 0x10 /* TX > 1 retries */
172 #define MREGS_TXFSTAT_ORETRY 0x08 /* TX 1 retry */
173 #define MREGS_TXFSTAT_PDEFER 0x04 /* TX pkt deferred */
174 #define MREGS_TXFSTAT_CLOSS 0x02 /* TX carrier lost */
175 #define MREGS_TXFSTAT_RERROR 0x01 /* TX retry error */
177 #define MREGS_TXRCNT_EDEFER 0x80 /* TX Excess defers */
178 #define MREGS_TXRCNT_CMASK 0x0f /* TX retry count */
180 #define MREGS_RXFCNTL_LOWLAT 0x08 /* RX low latency */
181 #define MREGS_RXFCNTL_AREJECT 0x04 /* RX addr match rej */
182 #define MREGS_RXFCNTL_AUTOSTRIP 0x01 /* RX auto strip */
184 #define MREGS_RXFSTAT_OVERFLOW 0x80 /* RX overflow */
185 #define MREGS_RXFSTAT_LCOLL 0x40 /* RX late collision */
186 #define MREGS_RXFSTAT_FERROR 0x20 /* RX framing error */
187 #define MREGS_RXFSTAT_FCSERROR 0x10 /* RX FCS error */
188 #define MREGS_RXFSTAT_RBCNT 0x0f /* RX msg byte count */
190 #define MREGS_FFCNT_RX 0xf0 /* RX FIFO frame cnt */
191 #define MREGS_FFCNT_TX 0x0f /* TX FIFO frame cnt */
199 #define MREGS_IREG_RXIRQ 0x02 /* IRQ RX'd a packet */
200 #define MREGS_IREG_TXIRQ 0x01 /* IRQ TX'd a packet */
205 #define MREGS_IMASK_RXIRQ 0x02 /* IMASK RX interrupts */
206 #define MREGS_IMASK_TXIRQ 0x01 /* IMASK TX interrupts */
208 #define MREGS_POLL_TXVALID 0x80 /* TX is valid */
209 #define MREGS_POLL_TDTR 0x40 /* TX data transfer request */
210 #define MREGS_POLL_RDTR 0x20 /* RX data transfer request */
217 #define MREGS_BCONFIG_RESET 0x01 /* SW-Reset the MACE */
219 #define MREGS_FCONFIG_TXF8 0x00 /* TX fifo 8 write cycles */
220 #define MREGS_FCONFIG_TXF32 0x80 /* TX fifo 32 write cycles */
221 #define MREGS_FCONFIG_TXF16 0x40 /* TX fifo 16 write cycles */
222 #define MREGS_FCONFIG_RXF64 0x20 /* RX fifo 64 write cycles */
223 #define MREGS_FCONFIG_RXF32 0x10 /* RX fifo 32 write cycles */
224 #define MREGS_FCONFIG_RXF16 0x00 /* RX fifo 16 write cycles */
225 #define MREGS_FCONFIG_TFWU 0x08 /* TX fifo watermark update */
226 #define MREGS_FCONFIG_RFWU 0x04 /* RX fifo watermark update */
227 #define MREGS_FCONFIG_TBENAB 0x02 /* TX burst enable */
228 #define MREGS_FCONFIG_RBENAB 0x01 /* RX burst enable */
231 #define MREGS_MCONFIG_TPDDISAB 0x40 /* TX 2part deferral enable */
233 #define MREGS_MCONFIG_RPADISAB 0x08 /* RX physical addr disable */
234 #define MREGS_MCONFIG_RBDISAB 0x04 /* RX broadcast disable */
238 #define MREGS_PLSCONFIG_TXMS 0x08 /* TX mode select */
247 #define MREGS_PHYCONFIG_RXPOLARITY 0x20 /* RX polarity */
250 #define MREGS_PHYCONFIG_AUTO 0x04 /* Connector port auto-sel */
262 #define MREGS_UTEST_FCSENAB 0x08 /* Enable FCS on RX */
294 #define NEXT_RX(num) (((num) + 1) & (RX_RING_MAXSIZE - 1))
295 #define NEXT_TX(num) (((num) + 1) & (TX_RING_MAXSIZE - 1))
296 #define PREV_RX(num) (((num) - 1) & (RX_RING_MAXSIZE - 1))
297 #define PREV_TX(num) (((num) - 1) & (TX_RING_MAXSIZE - 1))
300 (((qp)->tx_old <= (qp)->tx_new) ? \
301 (qp)->tx_old + (TX_RING_SIZE - 1) - (qp)->tx_new : \
302 (qp)->tx_old - (qp)->tx_new - 1)
310 ((__u32)((unsigned long)(&(((struct qe_init_block *)0)->mem[elem]))))
332 ((__u32)((unsigned long)(&(((struct sunqe_buffers *)0)->mem[elem][0]))))
335 void __iomem *qcregs; /* QEC per-channel Registers */
336 void __iomem *mregs; /* Per-channel MACE Registers */
337 struct qe_init_block *qe_block; /* RX and TX descriptors */
338 dma_addr_t qblock_dvma; /* RX and TX descriptors */
340 int rx_new, rx_old; /* RX ring extents */
341 int tx_new, tx_old; /* TX ring extents */