Lines Matching +full:address +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Reading this register automatically clears bits 0 through 6.
39 * This auto-clearing does not occur when the alias at GREG_STAT2
40 * is read instead. The rest of the interrupt bits only clear when
68 * Bits set in GREG_IMASK will prevent that interrupt type from being
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
70 * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6.
71 * Setting the bit will clear that interrupt, clear bits will have no effect
81 * Bits set in GREG_PCIEMASK will prevent that interrupt type from being
98 * The driver _MUST_ poll these bits until they clear. One may not attempt
99 * to program any other part of GEM until the bits clear.
121 #define TXDMA_FADDR 0x2104UL /* TX FIFO Address */
130 * This 13-bit register is programmed by the driver to hold the descriptor
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
165 * These two registers store the 53 most significant bits of the base address
166 * of the TX descriptor table. The 11 least significant bits are always
171 * them later. -DaveM
210 #define RXDMA_FADDR 0x410CUL /* RX FIFO Address */
220 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
221 #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
222 #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
223 #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
224 #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */
225 #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */
226 #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */
227 #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */
228 #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */
233 #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */
234 #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */
235 #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */
236 #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */
237 #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */
238 #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */
242 * These two registers store the 53 most significant bits of the base address
243 * of the RX descriptor table. The 11 least significant bits are always
257 * This 13-bit register is written by the host CPU and holds the last
270 * This 13-bit register is updated by GEM to indicate which RX descriptors
291 * This 11-bit read-only register indicates how large, in units of 64-bytes,
297 * them later. -DaveM
324 #define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */
325 #define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */
326 #define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */
327 #define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */
328 #define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */
329 #define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */
330 #define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */
331 #define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */
332 #define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */
333 #define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */
334 #define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */
335 #define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */
336 #define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */
337 #define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */
369 #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */
372 #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */
376 * Send_Pause and flow-control
411 * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent
414 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
420 * zero before any other bits in this register are changed.
425 * mode must be enabled when in half-duplex at 1Gbps, else
442 * zero before any other bits in this register are changed.
445 * programming the hash table registers, and the Address Filter
446 * Enable bit when programming the address filter registers.
454 #define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */
476 /* InterPacketGap0 Register. This 8-bit value is used as an extension
478 * timing of the RX-to-TX IPG. This value is ignored and presumed to
479 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
487 /* InterPacketGap1 Register. This 8-bit value defines the first 2/3
495 /* InterPacketGap2 Register. This 8-bit value defines the second 1/3
503 /* Slot Time Register. This 10-bit value specifies the slot time
510 /* Minimum Frame Size Register. This 10-bit register specifies the
522 * packets sent in half-duplex gigabit modes.
529 /* PA Size Register. This 10-bit register specifies the number of preamble
536 /* Jam Size Register. This 4-bit register specifies the duration of
542 /* Attempts Limit Register. This 8-bit register specifies the number
546 * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC
552 /* MAX Control Type Register. This 16-bit register specifies the
561 /* MAC Address Registers. Each of these registers specify the
562 * ethernet MAC of the interface, 16-bits at a time. Register
563 * 0 specifies bits [47:32], register 1 bits [31:16], and register
564 * 2 bits [15:0].
567 * MAC address for the interface.
570 * Address, which must be the reserved multicast address for MAC
573 * Example: To program primary station address a:b:c:d:e:f into
580 /* Address Filter Registers. Registers 0 through 2 specify bit
581 * fields [47:32] through [15:0], respectively, of the address
582 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
583 * nibble mask for Address Filter Registers 2 and 1. The Address
584 * Filter 0 Mask Register denotes the 16-bit mask for the Address
592 /* Statistics Registers. All of these registers are 16-bits and
599 /* Random Number Seed Register. This 10-bit value is used as the
602 * interfaces MAC address.
605 /* Pause Timer, read-only. This 16-bit timer is used to time the pause
607 * A non-zero value in this timer indicates that the MAC is currently in
612 #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */
613 #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */
614 #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */
621 /* MIF Bit-Bang Clock. This 1-bit register is used to generate the
623 * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into
630 /* MIF Bit-Bang Data. This 1-bit register is used to generate the
632 * is programmed in the "Bit-Bang" mode. The daa will be steered to the
637 /* MIF Big-Band Output Enable. THis 1-bit register is used to enable
638 * ('1') or disable ('0') the I-directional driver on the MII when the
639 * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled
640 * when data bits are transferred from the MIF to the transceiver, and it
641 * should be disabled when the interface is idle or when data bits are
647 /* MIF Configuration Register. This 15-bit register controls the operation
652 #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */
653 #define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */
654 #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
655 #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
656 #define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */
658 /* MIF Frame/Output Register. This 32-bit register allows the host to
659 * communicate with a transceiver in frame mode (as opposed to big-bang
667 #define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */
668 #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */
674 * operating in the poll mode. The poll status field is auto-clearing
678 #define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */
680 /* MIF Mask Register. This 16-bit register is used when in poll mode
681 * to say which bits of the polled register will cause an interrupt
702 #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */
705 #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */
707 #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit
716 #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */
718 #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */
727 #define PCS_MIIADV_ACK 0x00004000 /* Read-only */
728 #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */
741 #define PCS_CFG_JS 0x00000018 /* Jitter-study:
743 * 1 = high-frequency test pattern
744 * 2 = low-frequency test pattern
747 #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */
749 /* PCS Interrupt Status Register. This register is self-clearing
769 #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */
776 * test outputs into the PROM address pins. Set to zero for normal
779 #define PCS_SOS_PADDR 0x00000003 /* PROM Address */
802 /* MII BCM5201 MULTIPHY register bits */
806 /* MII BCM5400 1000-BASET Control register */
823 * control word. The same functionality is obtained via the TX-Kick
824 * and TX-Complete registers. As a result, GEM need not write back
828 * use the buffer DMA address as a place to keep track of allocated
859 * truly ready and that the ownership bits are set properly.
862 * buffer DMA address field will stay the same when it performs these
871 #define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */
880 ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
930 #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))
931 #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))
934 (((GP)->tx_old <= (GP)->tx_new) ? \
935 (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \
936 (GP)->tx_old - (GP)->tx_new - 1)
939 #define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)
981 unsigned int has_wol : 1; /* chip supports wake-on-lan */
1025 #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \
1026 gp->phy_mii.def && gp->phy_mii.def->ops)