Lines Matching full:register
12 #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
13 #define GREG_CFG 0x0004UL /* Configuration Register */
14 #define GREG_STAT 0x000CUL /* Status Register */
15 #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
16 #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
18 #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
19 #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
20 #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */
21 #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */
22 #define GREG_SWRST 0x1010UL /* Software Reset Register */
24 /* Global SEB State Register */
28 /* Global Configuration Register */
36 /* Global Interrupt Status Register.
38 * Reading this register automatically clears bits 0 through 6.
41 * the secondary interrupt status register corresponding to that
75 /* Global PCI Error Status Register */
85 /* Global BIF Configuration Register */
90 /* Global BIF Diagnostics Register */
94 /* Global Software Reset Register.
96 * This register is used to perform a global reset of the RX and TX portions
108 #define TXDMA_KICK 0x2000UL /* TX Kick Register */
109 #define TXDMA_CFG 0x2004UL /* TX Configuration Register */
117 #define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */
120 #define TXDMA_TXDONE 0x2100UL /* TX Completion Register */
128 /* TX Kick Register.
130 * This 13-bit register is programmed by the driver to hold the descriptor
134 /* TX Completion Register.
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
139 * access this register in the driver during interrupt processing.
142 /* TX Configuration Register.
181 /* WOL Match count register
196 #define RXDMA_CFG 0x4000UL /* RX Configuration Register */
203 #define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */
207 #define RXDMA_KICK 0x4100UL /* RX Kick Register */
208 #define RXDMA_DONE 0x4104UL /* RX Completion Register */
209 #define RXDMA_BLANK 0x4108UL /* RX Blanking Register */
217 /* RX Configuration Register. */
255 /* RX Kick Register.
257 * This 13-bit register is written by the host CPU and holds the last
259 * this register, it means that all RX descriptors up to but excluding
268 /* RX Completion Register.
270 * This 13-bit register is updated by GEM to indicate which RX descriptors
272 * excluding the value in this register are ready to be processed. GEM
273 * updates this register value after the RX FIFO empties completely into
275 * interrupt status register.
278 /* RX Blanking Register. */
291 * This 11-bit read-only register indicates how large, in units of 64-bytes,
303 #define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */
304 #define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */
305 #define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */
306 #define MAC_CSTAT 0x6018UL /* MAC Control Status Register */
307 #define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */
308 #define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */
309 #define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */
310 #define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/
311 #define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/
312 #define MAC_MCCFG 0x6038UL /* MAC Control Config Register */
313 #define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */
314 #define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */
315 #define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */
316 #define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */
317 #define MAC_STIME 0x604CUL /* SlotTime Register */
318 #define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */
319 #define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */
320 #define MAC_PASIZE 0x6058UL /* PA Size Register */
321 #define MAC_JAMSIZE 0x605CUL /* JamSize Register */
322 #define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */
323 #define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */
324 #define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */
325 #define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */
326 #define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */
327 #define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */
328 #define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */
329 #define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */
330 #define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */
331 #define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */
332 #define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */
333 #define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */
334 #define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */
335 #define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */
338 #define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */
339 #define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */
340 #define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */
341 #define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */
342 #define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */
343 #define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */
344 #define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */
345 #define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */
346 #define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */
347 #define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */
348 #define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */
349 #define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */
350 #define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */
351 #define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */
352 #define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */
353 #define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */
359 #define MAC_PATMPS 0x6114UL /* Peak Attempts Register */
365 #define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */
366 #define MAC_SMACHINE 0x6134UL /* State Machine Register */
384 /* TX MAC Status Register. */
395 /* RX MAC Status Register. */
404 /* MAC Control Status Register. */
417 /* TX MAC Configuration Register.
420 * zero before any other bits in this register are changed.
439 /* RX MAC Configuration Register.
442 * zero before any other bits in this register are changed.
458 /* MAC Control Config Register. */
463 /* XIF Configuration Register.
476 /* InterPacketGap0 Register. This 8-bit value is used as an extension
477 * to the InterPacketGap1 Register. Specifically it contributes to the
480 * is cleared in the TX MAC Configuration Register.
482 * This value in this register in terms of media byte time.
487 /* InterPacketGap1 Register. This 8-bit value defines the first 2/3
490 * This value in this register in terms of media byte time.
495 /* InterPacketGap2 Register. This 8-bit value defines the second 1/3
498 * This value in this register in terms of media byte time.
503 /* Slot Time Register. This 10-bit value specifies the slot time
510 /* Minimum Frame Size Register. This 10-bit register specifies the
517 /* Maximum Frame and Burst Size Register.
519 * This register specifies two things. First it specifies the maximum
529 /* PA Size Register. This 10-bit register specifies the number of preamble
536 /* Jam Size Register. This 4-bit register specifies the duration of
542 /* Attempts Limit Register. This 8-bit register specifies the number
547 * Configuration Register.
552 /* MAX Control Type Register. This 16-bit register specifies the
562 * ethernet MAC of the interface, 16-bits at a time. Register
563 * 0 specifies bits [47:32], register 1 bits [31:16], and register
582 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
584 * Filter 0 Mask Register denotes the 16-bit mask for the Address
585 * Filter Register 0.
599 /* Random Number Seed Register. This 10-bit value is used as the
601 * recommended to program this register to the 10 LSB of the
615 #define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */
616 #define MIF_CFG 0x6210UL /* MIF Configuration Register */
617 #define MIF_MASK 0x6214UL /* MIF Mask Register */
618 #define MIF_STATUS 0x6218UL /* MIF Status Register */
619 #define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */
621 /* MIF Bit-Bang Clock. This 1-bit register is used to generate the
624 * this register will create a rising edge on the MDC, while writing
630 /* MIF Bit-Bang Data. This 1-bit register is used to generate the
634 * Configuration Register.
637 /* MIF Big-Band Output Enable. THis 1-bit register is used to enable
644 * on the state of the PHY_Select bit in the MIF Configuration Register.
647 /* MIF Configuration Register. This 15-bit register controls the operation
653 #define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */
658 /* MIF Frame/Output Register. This 32-bit register allows the host to
661 * the host must poll this register for completion. Also, after
662 * completion this register holds the data returned by the transceiver
668 #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */
673 /* MIF Status Register. This register reports status when the MIF is
680 /* MIF Mask Register. This 16-bit register is used when in poll mode
681 * to say which bits of the polled register will cause an interrupt
686 #define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */
687 #define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */
690 #define PCS_CFG 0x9010UL /* PCS Configuration Register */
691 #define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */
693 #define PCS_DMODE 0x9050UL /* Datapath Mode Register */
694 #define PCS_SCTRL 0x9054UL /* Serialink Control Register */
696 #define PCS_SSTATE 0x905CUL /* Serialink State Register */
698 /* PCD MII Control Register. */
712 /* PCS MII Status Register. */
721 /* PCS MII Advertisement Register. */
730 /* PCS MII Link Partner Ability Register. This register is equivalent
731 * to the Link Partnet Ability Register of the standard MII register set.
732 * It's layout corresponds to the PCS MII Advertisement Register.
735 /* PCS Configuration Register. */
749 /* PCS Interrupt Status Register. This register is self-clearing
754 /* Datapath Mode Register. */
760 /* Serialink Control Register.
775 /* Shared Output Select Register. For test and debug, allows multiplexing
793 /* MII BCM5201 MULTIPHY interrupt register */
802 /* MII BCM5201 MULTIPHY register bits */
806 /* MII BCM5400 1000-BASET Control register */
810 /* MII BCM5400 AUXCONTROL register */
814 /* MII BCM5400 AUXSTATUS register */
858 * RX Kick register) by the driver it must make sure the buffers are