1 // SPDX-License-Identifier: GPL-2.0-only
5   Copyright (C) 2007-2014  STMicroelectronics Ltd
18 	unsigned int tdes0 = le32_to_cpu(p->des0);  in enh_desc_get_tx_status()
31 			x->tx_jabber++;  in enh_desc_get_tx_status()
34 			x->tx_frame_flushed++;  in enh_desc_get_tx_status()
39 			x->tx_losscarrier++;  in enh_desc_get_tx_status()
42 			x->tx_carrier++;  in enh_desc_get_tx_status()
46 			x->tx_collision +=  in enh_desc_get_tx_status()
50 			x->tx_deferred++;  in enh_desc_get_tx_status()
54 			x->tx_underflow++;  in enh_desc_get_tx_status()
58 			x->tx_ip_header_error++;  in enh_desc_get_tx_status()
61 			x->tx_payload_error++;  in enh_desc_get_tx_status()
69 		x->tx_deferred++;  in enh_desc_get_tx_status()
73 		x->tx_vlan++;  in enh_desc_get_tx_status()
81 	return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);  in enh_desc_get_tx_len()
90 	 * ----------------------------------------------------------  in enh_desc_coe_rdes0()
96 	 *      0 0 1 | IPv4/6 unsupported IP PAYLOAD  in enh_desc_coe_rdes0()
97 	 *      0 1 1 | COE bypassed.. no IPv4/6 frame  in enh_desc_coe_rdes0()
120 	unsigned int rdes0 = le32_to_cpu(p->basic.des0);  in enh_desc_get_ext_status()
121 	unsigned int rdes4 = le32_to_cpu(p->des4);  in enh_desc_get_ext_status()
127 			x->ip_hdr_err++;  in enh_desc_get_ext_status()
129 			x->ip_payload_err++;  in enh_desc_get_ext_status()
131 			x->ip_csum_bypassed++;  in enh_desc_get_ext_status()
133 			x->ipv4_pkt_rcvd++;  in enh_desc_get_ext_status()
135 			x->ipv6_pkt_rcvd++;  in enh_desc_get_ext_status()
138 			x->no_ptp_rx_msg_type_ext++;  in enh_desc_get_ext_status()
140 			x->ptp_rx_msg_type_sync++;  in enh_desc_get_ext_status()
142 			x->ptp_rx_msg_type_follow_up++;  in enh_desc_get_ext_status()
144 			x->ptp_rx_msg_type_delay_req++;  in enh_desc_get_ext_status()
146 			x->ptp_rx_msg_type_delay_resp++;  in enh_desc_get_ext_status()
148 			x->ptp_rx_msg_type_pdelay_req++;  in enh_desc_get_ext_status()
150 			x->ptp_rx_msg_type_pdelay_resp++;  in enh_desc_get_ext_status()
152 			x->ptp_rx_msg_type_pdelay_follow_up++;  in enh_desc_get_ext_status()
154 			x->ptp_rx_msg_type_announce++;  in enh_desc_get_ext_status()
156 			x->ptp_rx_msg_type_management++;  in enh_desc_get_ext_status()
158 			x->ptp_rx_msg_pkt_reserved_type++;  in enh_desc_get_ext_status()
161 			x->ptp_frame_type++;  in enh_desc_get_ext_status()
163 			x->ptp_ver++;  in enh_desc_get_ext_status()
165 			x->timestamp_dropped++;  in enh_desc_get_ext_status()
167 			x->av_pkt_rcvd++;  in enh_desc_get_ext_status()
169 			x->av_tagged_pkt_rcvd++;  in enh_desc_get_ext_status()
171 			x->vlan_tag_priority_val++;  in enh_desc_get_ext_status()
173 			x->l3_filter_match++;  in enh_desc_get_ext_status()
175 			x->l4_filter_match++;  in enh_desc_get_ext_status()
177 			x->l3_l4_filter_no_match++;  in enh_desc_get_ext_status()
184 	unsigned int rdes0 = le32_to_cpu(p->des0);  in enh_desc_get_rx_status()
191 		x->rx_length++;  in enh_desc_get_rx_status()
197 			x->rx_desc++;  in enh_desc_get_rx_status()
198 			x->rx_length++;  in enh_desc_get_rx_status()
201 			x->rx_gmac_overflow++;  in enh_desc_get_rx_status()
207 			x->rx_collision++;  in enh_desc_get_rx_status()
209 			x->rx_watchdog++;  in enh_desc_get_rx_status()
212 			x->rx_mii++;  in enh_desc_get_rx_status()
215 			x->rx_crc_errors++;  in enh_desc_get_rx_status()
230 		x->dribbling_bit++;  in enh_desc_get_rx_status()
233 		x->sa_rx_filter_fail++;  in enh_desc_get_rx_status()
237 		x->da_rx_filter_fail++;  in enh_desc_get_rx_status()
241 		x->rx_length++;  in enh_desc_get_rx_status()
246 		x->rx_vlan++;  in enh_desc_get_rx_status()
257 	p->des0 |= cpu_to_le32(RDES0_OWN);  in enh_desc_init_rx_desc()
260 	p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK);  in enh_desc_init_rx_desc()
268 		p->des1 |= cpu_to_le32(ERDES1_DISABLE_IC);  in enh_desc_init_rx_desc()
273 	p->des0 &= cpu_to_le32(~ETDES0_OWN);  in enh_desc_init_tx_desc()
282 	return (le32_to_cpu(p->des0) & ETDES0_OWN) >> 31;  in enh_desc_get_tx_owner()
287 	p->des0 |= cpu_to_le32(ETDES0_OWN);  in enh_desc_set_tx_owner()
292 	p->des0 |= cpu_to_le32(RDES0_OWN);  in enh_desc_set_rx_owner()
297 	return (le32_to_cpu(p->des0) & ETDES0_LAST_SEGMENT) >> 29;  in enh_desc_get_tx_ls()
302 	int ter = (le32_to_cpu(p->des0) & ETDES0_END_RING) >> 21;  in enh_desc_release_tx_desc()
315 	unsigned int tdes0 = le32_to_cpu(p->des0);  in enh_desc_prepare_tx_desc()
346 	p->des0 = cpu_to_le32(tdes0);  in enh_desc_prepare_tx_desc()
351 	p->des0 |= cpu_to_le32(ETDES0_INTERRUPT);  in enh_desc_set_tx_ic()
357 	/* The type-1 checksum offload engines append the checksum at  in enh_desc_get_rx_frame_len()
360 	 * Adjust for that in the framelen for type-1 checksum offload  in enh_desc_get_rx_frame_len()
366 	return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)  in enh_desc_get_rx_frame_len()
367 				>> RDES0_FRAME_LEN_SHIFT) - csum);  in enh_desc_get_rx_frame_len()
372 	p->des0 |= cpu_to_le32(ETDES0_TIME_STAMP_ENABLE);  in enh_desc_enable_tx_timestamp()
377 	return (le32_to_cpu(p->des0) & ETDES0_TIME_STAMP_STATUS) >> 17;  in enh_desc_get_tx_timestamp_status()
386 		ns = le32_to_cpu(p->des6);  in enh_desc_get_timestamp()
388 		ns += le32_to_cpu(p->des7) * 1000000000ULL;  in enh_desc_get_timestamp()
391 		ns = le32_to_cpu(p->des2);  in enh_desc_get_timestamp()
392 		ns += le32_to_cpu(p->des3) * 1000000000ULL;  in enh_desc_get_timestamp()
403 		return (le32_to_cpu(p->basic.des0) & RDES0_IPC_CSUM_ERROR) >> 7;  in enh_desc_get_rx_timestamp_status()
406 		if ((le32_to_cpu(p->des2) == 0xffffffff) &&  in enh_desc_get_rx_timestamp_status()
407 		    (le32_to_cpu(p->des3) == 0xffffffff))  in enh_desc_get_rx_timestamp_status()
432 			ep->basic.des2, ep->basic.des3);  in enh_desc_display_ring()
440 	p->des2 = cpu_to_le32(addr);  in enh_desc_set_addr()
445 	p->des2 = 0;  in enh_desc_clear()