1 // SPDX-License-Identifier: GPL-2.0-only
3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
26 	if (axi->axi_lpi_en)  in dwmac4_dma_axi()
28 	if (axi->axi_xit_frm)  in dwmac4_dma_axi()
32 	value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<  in dwmac4_dma_axi()
36 	value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<  in dwmac4_dma_axi()
44 		switch (axi->axi_blen[i]) {  in dwmac4_dma_axi()
77 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_init_rx_chan()
79 	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;  in dwmac4_dma_init_rx_chan()
85 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))  in dwmac4_dma_init_rx_chan()
98 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_init_tx_chan()
100 	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;  in dwmac4_dma_init_tx_chan()
110 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))  in dwmac4_dma_init_tx_chan()
122 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_init_channel()
127 	if (dma_cfg->pblx8)  in dwmac4_dma_init_channel()
140 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac410_dma_init_channel()
145 	if (dma_cfg->pblx8)  in dwmac410_dma_init_channel()
161 	if (dma_cfg->fixed_burst)  in dwmac4_dma_init()
165 	if (dma_cfg->mixed_burst)  in dwmac4_dma_init()
168 	if (dma_cfg->aal)  in dwmac4_dma_init()
171 	if (dma_cfg->eame)  in dwmac4_dma_init()
178 	if (dma_cfg->multi_msi_en) {  in dwmac4_dma_init()
183 	if (dma_cfg->dche)  in dwmac4_dma_init()
194 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in _dwmac4_dump_dma_regs()
256 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_rx_watchdog()
265 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_rx_chan_op_mode()
266 	unsigned int rqs = fifosz / 256 - 1;  in dwmac4_dma_rx_chan_op_mode()
272 		pr_debug("GMAC: enable RX store and forward mode\n");  in dwmac4_dma_rx_chan_op_mode()
275 		pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);  in dwmac4_dma_rx_chan_op_mode()
310 			rfd = 0x03; /* Full-2.5K */  in dwmac4_dma_rx_chan_op_mode()
311 			rfa = 0x01; /* Full-1.5K */  in dwmac4_dma_rx_chan_op_mode()
315 			rfd = 0x07; /* Full-4.5K */  in dwmac4_dma_rx_chan_op_mode()
316 			rfa = 0x04; /* Full-3K */  in dwmac4_dma_rx_chan_op_mode()
334 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_dma_tx_chan_op_mode()
337 	unsigned int tqs = fifosz / 256 - 1;  in dwmac4_dma_tx_chan_op_mode()
340 		pr_debug("GMAC: enable TX store and forward mode\n");  in dwmac4_dma_tx_chan_op_mode()
341 		/* Transmit COE type 2 cannot be done in cut-through mode. */  in dwmac4_dma_tx_chan_op_mode()
344 		pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);  in dwmac4_dma_tx_chan_op_mode()
370 	 * TXQEN must be written for multi-channel operation and TQS must  in dwmac4_dma_tx_chan_op_mode()
391 	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);  in dwmac4_get_hw_feature()
392 	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;  in dwmac4_get_hw_feature()
393 	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;  in dwmac4_get_hw_feature()
394 	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;  in dwmac4_get_hw_feature()
395 	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;  in dwmac4_get_hw_feature()
396 	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;  in dwmac4_get_hw_feature()
397 	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;  in dwmac4_get_hw_feature()
398 	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;  in dwmac4_get_hw_feature()
399 	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;  in dwmac4_get_hw_feature()
401 	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;  in dwmac4_get_hw_feature()
402 	/* IEEE 1588-2008 */  in dwmac4_get_hw_feature()
403 	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;  in dwmac4_get_hw_feature()
404 	/* 802.3az - Energy-Efficient Ethernet (EEE) */  in dwmac4_get_hw_feature()
405 	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;  in dwmac4_get_hw_feature()
407 	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;  in dwmac4_get_hw_feature()
408 	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;  in dwmac4_get_hw_feature()
409 	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;  in dwmac4_get_hw_feature()
410 	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;  in dwmac4_get_hw_feature()
414 	dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;  in dwmac4_get_hw_feature()
415 	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;  in dwmac4_get_hw_feature()
416 	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;  in dwmac4_get_hw_feature()
417 	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;  in dwmac4_get_hw_feature()
418 	dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;  in dwmac4_get_hw_feature()
420 	dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;  in dwmac4_get_hw_feature()
421 	switch (dma_cap->addr64) {  in dwmac4_get_hw_feature()
423 		dma_cap->addr64 = 32;  in dwmac4_get_hw_feature()
426 		dma_cap->addr64 = 40;  in dwmac4_get_hw_feature()
429 		dma_cap->addr64 = 48;  in dwmac4_get_hw_feature()
432 		dma_cap->addr64 = 32;  in dwmac4_get_hw_feature()
439 	dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);  in dwmac4_get_hw_feature()
440 	dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);  in dwmac4_get_hw_feature()
444 	dma_cap->number_rx_channel =  in dwmac4_get_hw_feature()
446 	dma_cap->number_tx_channel =  in dwmac4_get_hw_feature()
449 	dma_cap->number_rx_queues =  in dwmac4_get_hw_feature()
451 	dma_cap->number_tx_queues =  in dwmac4_get_hw_feature()
454 	dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;  in dwmac4_get_hw_feature()
456 	/* IEEE 1588-2002 */  in dwmac4_get_hw_feature()
457 	dma_cap->time_stamp = 0;  in dwmac4_get_hw_feature()
459 	dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;  in dwmac4_get_hw_feature()
465 	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;  in dwmac4_get_hw_feature()
466 	dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;  in dwmac4_get_hw_feature()
467 	dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;  in dwmac4_get_hw_feature()
468 	dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;  in dwmac4_get_hw_feature()
469 	dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;  in dwmac4_get_hw_feature()
470 	dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;  in dwmac4_get_hw_feature()
471 	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;  in dwmac4_get_hw_feature()
472 	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;  in dwmac4_get_hw_feature()
473 	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;  in dwmac4_get_hw_feature()
474 	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;  in dwmac4_get_hw_feature()
483 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_enable_tso()
502 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_qmode()
518 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_set_bfsize()
530 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_enable_sph()
553 	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;  in dwmac4_enable_tbs()
566 		return -EIO;  in dwmac4_enable_tbs()