Lines Matching +full:dwmac +full:- +full:3

1 // SPDX-License-Identifier: GPL-2.0
24 #define ETHER_CLK_SEL_RMII_CLK_RST BIT(3)
58 struct visconti_eth *dwmac = bsp_priv; in visconti_eth_set_clk_tx_rate() local
76 return -EINVAL; in visconti_eth_set_clk_tx_rate()
80 val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
84 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
86 /* Set Clock-Mux, Start clock, Set TX_O direction */ in visconti_eth_set_clk_tx_rate()
88 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
91 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
94 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
106 return -EINVAL; in visconti_eth_set_clk_tx_rate()
110 val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
114 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
116 /* Set Clock-Mux, Start clock, Set TX_O direction */ in visconti_eth_set_clk_tx_rate()
121 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
124 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
127 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
130 val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
134 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
136 /* Set Clock-Mux, Start clock, Set TX_O direction */ in visconti_eth_set_clk_tx_rate()
140 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
143 writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_set_clk_tx_rate()
151 struct visconti_eth *dwmac = plat_dat->bsp_priv; in visconti_eth_init_hw() local
155 switch (plat_dat->phy_interface) { in visconti_eth_init_hw()
169 dev_err(&pdev->dev, "Unsupported phy-mode (%d)\n", plat_dat->phy_interface); in visconti_eth_init_hw()
170 return -EOPNOTSUPP; in visconti_eth_init_hw()
173 writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL); in visconti_eth_init_hw()
177 writel(clk_sel_val, dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_init_hw()
180 dwmac->reg + REG_ETHER_CLOCK_SEL); in visconti_eth_init_hw()
182 /* release internal-reset */ in visconti_eth_init_hw()
184 writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL); in visconti_eth_init_hw()
192 struct visconti_eth *dwmac = plat_dat->bsp_priv; in visconti_eth_clock_probe() local
195 dwmac->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref_clk"); in visconti_eth_clock_probe()
196 if (IS_ERR(dwmac->phy_ref_clk)) in visconti_eth_clock_probe()
197 return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->phy_ref_clk), in visconti_eth_clock_probe()
200 err = clk_prepare_enable(dwmac->phy_ref_clk); in visconti_eth_clock_probe()
202 dev_err(&pdev->dev, "failed to enable phy_ref clock: %d\n", err); in visconti_eth_clock_probe()
211 struct visconti_eth *dwmac = get_stmmac_bsp_priv(&pdev->dev); in visconti_eth_clock_remove() local
215 clk_disable_unprepare(dwmac->phy_ref_clk); in visconti_eth_clock_remove()
216 clk_disable_unprepare(priv->plat->stmmac_clk); in visconti_eth_clock_remove()
223 struct visconti_eth *dwmac; in visconti_eth_dwmac_probe() local
234 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); in visconti_eth_dwmac_probe()
235 if (!dwmac) in visconti_eth_dwmac_probe()
236 return -ENOMEM; in visconti_eth_dwmac_probe()
238 dwmac->reg = stmmac_res.addr; in visconti_eth_dwmac_probe()
239 dwmac->dev = &pdev->dev; in visconti_eth_dwmac_probe()
240 plat_dat->bsp_priv = dwmac; in visconti_eth_dwmac_probe()
241 plat_dat->set_clk_tx_rate = visconti_eth_set_clk_tx_rate; in visconti_eth_dwmac_probe()
249 plat_dat->dma_cfg->aal = 1; in visconti_eth_dwmac_probe()
251 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in visconti_eth_dwmac_probe()
270 { .compatible = "toshiba,visconti-dwmac" },
279 .name = "visconti-eth-dwmac",
286 MODULE_DESCRIPTION("Toshiba Visconti Ethernet DWMAC glue driver");