Lines Matching +full:rk3399 +full:- +full:grf
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
90 struct regmap *grf; member
103 val = rsd->rgmii_10; in rk_set_reg_speed()
105 val = rsd->rgmii_100; in rk_set_reg_speed()
107 val = rsd->rgmii_1000; in rk_set_reg_speed()
112 return -EINVAL; in rk_set_reg_speed()
116 val = rsd->rmii_10; in rk_set_reg_speed()
118 val = rsd->rmii_100; in rk_set_reg_speed()
123 return -EINVAL; in rk_set_reg_speed()
130 return -EINVAL; in rk_set_reg_speed()
133 regmap_write(bsp_priv->grf, reg, val); in rk_set_reg_speed()
142 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; in rk_set_clk_mac_speed()
176 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); in rk_gmac_integrated_ephy_powerup()
177 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); in rk_gmac_integrated_ephy_powerup()
179 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); in rk_gmac_integrated_ephy_powerup()
180 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); in rk_gmac_integrated_ephy_powerup()
182 if (priv->phy_reset) { in rk_gmac_integrated_ephy_powerup()
184 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); in rk_gmac_integrated_ephy_powerup()
185 if (priv->phy_reset) in rk_gmac_integrated_ephy_powerup()
186 reset_control_assert(priv->phy_reset); in rk_gmac_integrated_ephy_powerup()
188 if (priv->phy_reset) in rk_gmac_integrated_ephy_powerup()
189 reset_control_deassert(priv->phy_reset); in rk_gmac_integrated_ephy_powerup()
191 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); in rk_gmac_integrated_ephy_powerup()
198 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); in rk_gmac_integrated_ephy_powerdown()
199 if (priv->phy_reset) in rk_gmac_integrated_ephy_powerdown()
200 reset_control_assert(priv->phy_reset); in rk_gmac_integrated_ephy_powerdown()
212 reset_control_assert(priv->phy_reset); in rk_gmac_integrated_fephy_powerup()
215 regmap_write(priv->grf, reg, in rk_gmac_integrated_fephy_powerup()
222 reset_control_deassert(priv->phy_reset); in rk_gmac_integrated_fephy_powerup()
229 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); in rk_gmac_integrated_fephy_powerdown()
242 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_to_rmii()
249 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; in px30_set_speed()
250 struct device *dev = bsp_priv->dev; in px30_set_speed()
256 return -EINVAL; in px30_set_speed()
267 return -EINVAL; in px30_set_speed()
270 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1); in px30_set_speed()
311 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_to_rgmii()
314 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, in rk3128_set_to_rgmii()
322 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, in rk3128_set_to_rmii()
383 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_to_rgmii()
388 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, in rk3228_set_to_rgmii()
395 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, in rk3228_set_to_rmii()
400 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); in rk3228_set_to_rmii()
420 regmap_write(priv->grf, RK3228_GRF_CON_MUX, in rk3228_integrated_phy_powerup()
465 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_to_rgmii()
468 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, in rk3288_set_to_rgmii()
476 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, in rk3288_set_to_rmii()
513 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, in rk3308_set_to_rmii()
568 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, in rk3328_set_to_rgmii()
574 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, in rk3328_set_to_rgmii()
583 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : in rk3328_set_to_rmii()
586 regmap_write(bsp_priv->grf, reg, in rk3328_set_to_rmii()
604 if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy) in rk3328_set_speed()
615 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, in rk3328_integrated_phy_powerup()
660 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_to_rgmii()
663 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, in rk3366_set_to_rgmii()
671 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, in rk3366_set_to_rmii()
727 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_to_rgmii()
730 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, in rk3368_set_to_rgmii()
738 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, in rk3368_set_to_rmii()
794 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_to_rgmii()
797 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, in rk3399_set_to_rgmii()
798 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | in rk3399_set_to_rgmii()
805 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, in rk3399_set_to_rmii()
868 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, in rk3528_set_to_rgmii()
871 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, in rk3528_set_to_rgmii()
874 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, in rk3528_set_to_rgmii()
881 if (bsp_priv->id == 1) in rk3528_set_to_rmii()
882 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, in rk3528_set_to_rmii()
885 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, in rk3528_set_to_rmii()
909 if (bsp_priv->id == 1) { in rk3528_set_speed()
925 if (bsp_priv->id == 1) { in rk3528_set_clock_selection()
930 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); in rk3528_set_clock_selection()
934 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); in rk3528_set_clock_selection()
989 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : in rk3568_set_to_rgmii()
991 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : in rk3568_set_to_rgmii()
994 regmap_write(bsp_priv->grf, con0, in rk3568_set_to_rgmii()
998 regmap_write(bsp_priv->grf, con1, in rk3568_set_to_rgmii()
1008 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : in rk3568_set_to_rmii()
1010 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII); in rk3568_set_to_rmii()
1067 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_to_rgmii()
1070 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); in rk3576_set_to_rgmii()
1072 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : in rk3576_set_to_rgmii()
1076 regmap_write(bsp_priv->php_grf, offset_con, in rk3576_set_to_rgmii()
1078 regmap_write(bsp_priv->php_grf, offset_con + 0x4, in rk3576_set_to_rgmii()
1082 regmap_write(bsp_priv->php_grf, offset_con, in rk3576_set_to_rgmii()
1085 regmap_write(bsp_priv->php_grf, offset_con + 0x4, in rk3576_set_to_rgmii()
1094 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_to_rmii()
1097 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); in rk3576_set_to_rmii()
1113 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_gmac_speed()
1130 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : in rk3576_set_clock_selection()
1133 regmap_write(bsp_priv->grf, offset_con, val); in rk3576_set_clock_selection()
1194 u32 offset_con, id = bsp_priv->id; in rk3588_set_to_rgmii()
1196 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : in rk3588_set_to_rgmii()
1199 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, in rk3588_set_to_rgmii()
1202 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, in rk3588_set_to_rgmii()
1205 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7, in rk3588_set_to_rgmii()
1209 regmap_write(bsp_priv->grf, offset_con, in rk3588_set_to_rgmii()
1216 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, in rk3588_set_to_rmii()
1217 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); in rk3588_set_to_rmii()
1219 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, in rk3588_set_to_rmii()
1220 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); in rk3588_set_to_rmii()
1226 unsigned int val = 0, id = bsp_priv->id; in rk3588_set_gmac_speed()
1251 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); in rk3588_set_gmac_speed()
1255 return -EINVAL; in rk3588_set_gmac_speed()
1261 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) : in rk3588_set_clock_selection()
1262 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id); in rk3588_set_clock_selection()
1264 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : in rk3588_set_clock_selection()
1265 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); in rk3588_set_clock_selection()
1267 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); in rk3588_set_clock_selection()
1298 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, in rv1108_set_to_rmii()
1349 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, in rv1126_set_to_rgmii()
1356 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1, in rv1126_set_to_rgmii()
1360 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2, in rv1126_set_to_rgmii()
1367 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, in rv1126_set_to_rmii()
1379 struct rk_priv_data *bsp_priv = plat->bsp_priv; in rk_gmac_clk_init()
1380 int phy_iface = bsp_priv->phy_iface; in rk_gmac_clk_init()
1381 struct device *dev = bsp_priv->dev; in rk_gmac_clk_init()
1384 bsp_priv->clk_enabled = false; in rk_gmac_clk_init()
1386 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); in rk_gmac_clk_init()
1388 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); in rk_gmac_clk_init()
1390 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks, in rk_gmac_clk_init()
1391 sizeof(*bsp_priv->clks), GFP_KERNEL); in rk_gmac_clk_init()
1392 if (!bsp_priv->clks) in rk_gmac_clk_init()
1393 return -ENOMEM; in rk_gmac_clk_init()
1396 bsp_priv->clks[i].id = rk_clocks[i]; in rk_gmac_clk_init()
1400 bsp_priv->clks[i++].id = rk_rmii_clocks[j]; in rk_gmac_clk_init()
1403 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks, in rk_gmac_clk_init()
1404 bsp_priv->clks); in rk_gmac_clk_init()
1408 if (bsp_priv->clock_input) { in rk_gmac_clk_init()
1411 clk_set_rate(plat->stmmac_clk, 50000000); in rk_gmac_clk_init()
1414 if (plat->phy_node && bsp_priv->integrated_phy) { in rk_gmac_clk_init()
1415 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); in rk_gmac_clk_init()
1416 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); in rk_gmac_clk_init()
1419 clk_set_rate(bsp_priv->clk_phy, 50000000); in rk_gmac_clk_init()
1430 if (!bsp_priv->clk_enabled) { in gmac_clk_enable()
1431 ret = clk_bulk_prepare_enable(bsp_priv->num_clks, in gmac_clk_enable()
1432 bsp_priv->clks); in gmac_clk_enable()
1436 ret = clk_prepare_enable(bsp_priv->clk_phy); in gmac_clk_enable()
1440 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) in gmac_clk_enable()
1441 bsp_priv->ops->set_clock_selection(bsp_priv, in gmac_clk_enable()
1442 bsp_priv->clock_input, true); in gmac_clk_enable()
1445 bsp_priv->clk_enabled = true; in gmac_clk_enable()
1448 if (bsp_priv->clk_enabled) { in gmac_clk_enable()
1449 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) { in gmac_clk_enable()
1450 bsp_priv->ops->set_clock_selection(bsp_priv, in gmac_clk_enable()
1451 bsp_priv->clock_input, false); in gmac_clk_enable()
1454 clk_bulk_disable_unprepare(bsp_priv->num_clks, in gmac_clk_enable()
1455 bsp_priv->clks); in gmac_clk_enable()
1456 clk_disable_unprepare(bsp_priv->clk_phy); in gmac_clk_enable()
1458 bsp_priv->clk_enabled = false; in gmac_clk_enable()
1467 struct regulator *ldo = bsp_priv->regulator; in phy_power_on()
1468 struct device *dev = bsp_priv->dev; in phy_power_on()
1474 dev_err(dev, "fail to enable phy-supply\n"); in phy_power_on()
1478 dev_err(dev, "fail to disable phy-supply\n"); in phy_power_on()
1489 struct device *dev = &pdev->dev; in rk_gmac_setup()
1497 return ERR_PTR(-ENOMEM); in rk_gmac_setup()
1499 bsp_priv->phy_iface = plat->phy_interface; in rk_gmac_setup()
1500 bsp_priv->ops = ops; in rk_gmac_setup()
1506 if (res && ops->regs_valid) { in rk_gmac_setup()
1509 while (ops->regs[i]) { in rk_gmac_setup()
1510 if (ops->regs[i] == res->start) { in rk_gmac_setup()
1511 bsp_priv->id = i; in rk_gmac_setup()
1518 bsp_priv->regulator = devm_regulator_get(dev, "phy"); in rk_gmac_setup()
1519 if (IS_ERR(bsp_priv->regulator)) { in rk_gmac_setup()
1520 ret = PTR_ERR(bsp_priv->regulator); in rk_gmac_setup()
1525 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); in rk_gmac_setup()
1528 bsp_priv->clock_input = true; in rk_gmac_setup()
1533 bsp_priv->clock_input = true; in rk_gmac_setup()
1535 bsp_priv->clock_input = false; in rk_gmac_setup()
1538 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); in rk_gmac_setup()
1540 bsp_priv->tx_delay = 0x30; in rk_gmac_setup()
1543 bsp_priv->tx_delay); in rk_gmac_setup()
1546 bsp_priv->tx_delay = value; in rk_gmac_setup()
1549 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); in rk_gmac_setup()
1551 bsp_priv->rx_delay = 0x10; in rk_gmac_setup()
1554 bsp_priv->rx_delay); in rk_gmac_setup()
1557 bsp_priv->rx_delay = value; in rk_gmac_setup()
1560 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rk_gmac_setup()
1561 "rockchip,grf"); in rk_gmac_setup()
1562 if (IS_ERR(bsp_priv->grf)) { in rk_gmac_setup()
1563 dev_err_probe(dev, PTR_ERR(bsp_priv->grf), in rk_gmac_setup()
1564 "failed to lookup rockchip,grf\n"); in rk_gmac_setup()
1565 return ERR_CAST(bsp_priv->grf); in rk_gmac_setup()
1568 if (ops->php_grf_required) { in rk_gmac_setup()
1569 bsp_priv->php_grf = in rk_gmac_setup()
1570 syscon_regmap_lookup_by_phandle(dev->of_node, in rk_gmac_setup()
1571 "rockchip,php-grf"); in rk_gmac_setup()
1572 if (IS_ERR(bsp_priv->php_grf)) { in rk_gmac_setup()
1573 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf), in rk_gmac_setup()
1574 "failed to lookup rockchip,php-grf\n"); in rk_gmac_setup()
1575 return ERR_CAST(bsp_priv->php_grf); in rk_gmac_setup()
1579 if (plat->phy_node) { in rk_gmac_setup()
1580 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, in rk_gmac_setup()
1581 "phy-is-integrated"); in rk_gmac_setup()
1582 if (bsp_priv->integrated_phy) { in rk_gmac_setup()
1583 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); in rk_gmac_setup()
1584 if (IS_ERR(bsp_priv->phy_reset)) { in rk_gmac_setup()
1585 dev_err(&pdev->dev, "No PHY reset control found.\n"); in rk_gmac_setup()
1586 bsp_priv->phy_reset = NULL; in rk_gmac_setup()
1591 bsp_priv->integrated_phy ? "yes" : "no"); in rk_gmac_setup()
1593 bsp_priv->dev = dev; in rk_gmac_setup()
1600 switch (bsp_priv->phy_iface) { in rk_gmac_check_ops()
1605 if (!bsp_priv->ops->set_to_rgmii) in rk_gmac_check_ops()
1606 return -EINVAL; in rk_gmac_check_ops()
1609 if (!bsp_priv->ops->set_to_rmii) in rk_gmac_check_ops()
1610 return -EINVAL; in rk_gmac_check_ops()
1613 dev_err(bsp_priv->dev, in rk_gmac_check_ops()
1614 "unsupported interface %d", bsp_priv->phy_iface); in rk_gmac_check_ops()
1621 struct device *dev = bsp_priv->dev; in rk_gmac_powerup()
1633 switch (bsp_priv->phy_iface) { in rk_gmac_powerup()
1636 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, in rk_gmac_powerup()
1637 bsp_priv->rx_delay); in rk_gmac_powerup()
1641 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); in rk_gmac_powerup()
1645 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); in rk_gmac_powerup()
1649 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); in rk_gmac_powerup()
1653 bsp_priv->ops->set_to_rmii(bsp_priv); in rk_gmac_powerup()
1667 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) in rk_gmac_powerup()
1668 bsp_priv->ops->integrated_phy_powerup(bsp_priv); in rk_gmac_powerup()
1675 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown) in rk_gmac_powerdown()
1676 gmac->ops->integrated_phy_powerdown(gmac); in rk_gmac_powerdown()
1678 pm_runtime_put_sync(gmac->dev); in rk_gmac_powerdown()
1689 if (rk->ops->set_to_rgmii) in rk_get_interfaces()
1692 if (rk->ops->set_to_rmii) in rk_get_interfaces()
1701 if (bsp_priv->ops->set_speed) in rk_set_clk_tx_rate()
1702 return bsp_priv->ops->set_speed(bsp_priv, bsp_priv->phy_iface, in rk_set_clk_tx_rate()
1705 return -EINVAL; in rk_set_clk_tx_rate()
1712 /* Keep the PHY up if we use Wake-on-Lan. */ in rk_gmac_suspend()
1723 /* The PHY was up for Wake-on-Lan. */ in rk_gmac_resume()
1737 data = of_device_get_match_data(&pdev->dev); in rk_gmac_probe()
1739 dev_err(&pdev->dev, "no of match data provided\n"); in rk_gmac_probe()
1740 return -EINVAL; in rk_gmac_probe()
1754 if (!plat_dat->has_gmac4) { in rk_gmac_probe()
1755 plat_dat->has_gmac = true; in rk_gmac_probe()
1756 plat_dat->rx_fifo_size = 4096; in rk_gmac_probe()
1757 plat_dat->tx_fifo_size = 2048; in rk_gmac_probe()
1760 plat_dat->get_interfaces = rk_get_interfaces; in rk_gmac_probe()
1761 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate; in rk_gmac_probe()
1762 plat_dat->suspend = rk_gmac_suspend; in rk_gmac_probe()
1763 plat_dat->resume = rk_gmac_resume; in rk_gmac_probe()
1765 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); in rk_gmac_probe()
1766 if (IS_ERR(plat_dat->bsp_priv)) in rk_gmac_probe()
1767 return PTR_ERR(plat_dat->bsp_priv); in rk_gmac_probe()
1773 ret = rk_gmac_powerup(plat_dat->bsp_priv); in rk_gmac_probe()
1777 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in rk_gmac_probe()
1784 rk_gmac_powerdown(plat_dat->bsp_priv); in rk_gmac_probe()
1792 struct rk_priv_data *bsp_priv = priv->plat->bsp_priv; in rk_gmac_remove()
1794 stmmac_dvr_remove(&pdev->dev); in rk_gmac_remove()
1798 if (priv->plat->phy_node && bsp_priv->integrated_phy) in rk_gmac_remove()
1799 clk_put(bsp_priv->clk_phy); in rk_gmac_remove()
1803 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
1804 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1805 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1806 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1807 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1808 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1809 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1810 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1811 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1812 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
1813 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1814 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
1815 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
1816 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1817 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
1826 .name = "rk_gmac-dwmac",
1833 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");