Lines Matching +full:clock +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
94 /* clock ids to be requested */
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
119 switch (plat->phy_mode) {
133 dev_err(plat->dev, "phy interface not supported\n");
134 return -EINVAL;
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
144 struct mac_delay_struct *mac_delay = &plat->mac_delay;
146 switch (plat->phy_mode) {
150 mac_delay->tx_delay /= 550;
151 mac_delay->rx_delay /= 550;
158 mac_delay->tx_delay /= 170;
159 mac_delay->rx_delay /= 170;
162 dev_err(plat->dev, "phy interface not supported\n");
169 struct mac_delay_struct *mac_delay = &plat->mac_delay;
171 switch (plat->phy_mode) {
175 mac_delay->tx_delay *= 550;
176 mac_delay->rx_delay *= 550;
183 mac_delay->tx_delay *= 170;
184 mac_delay->rx_delay *= 170;
187 dev_err(plat->dev, "phy interface not supported\n");
194 struct mac_delay_struct *mac_delay = &plat->mac_delay;
199 switch (plat->phy_mode) {
201 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
202 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay);
203 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv);
205 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
206 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
207 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
210 if (plat->rmii_clk_from_mac) {
211 /* case 1: mac provides the rmii reference clock,
212 * and the clock output to TXC pin.
213 * The egress timing can be adjusted by GTXC delay macro circuit.
214 * The ingress timing can be adjusted by TXC delay macro circuit.
216 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
217 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
218 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
220 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
221 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
222 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
224 /* case 2: the rmii reference clock is from external phy,
226 * the reference clk is connected to. The reference clock is a
228 * the reference clock timing adjustment
230 if (plat->rmii_rxc) {
231 /* the rmii reference clock from outside is connected
232 * to RXC pin, the reference clock will be adjusted
233 * by RXC delay macro circuit.
235 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
236 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
237 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
239 /* the rmii reference clock from outside is connected
240 * to TXC pin, the reference clock will be adjusted
241 * by TXC delay macro circuit.
243 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
244 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
245 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
247 /* tx_inv will inverse the tx clock inside mac relateive to
248 * reference clock from external phy,
249 * and this bit is located in the same register with fine-tune
251 if (mac_delay->tx_inv)
261 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
262 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
263 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
265 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
266 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
267 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
270 dev_err(plat->dev, "phy interface not supported\n");
271 return -EINVAL;
273 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
274 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
293 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
294 int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
298 switch (plat->phy_mode) {
313 dev_err(plat->dev, "phy interface not supported\n");
314 return -EINVAL;
320 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val);
327 struct mac_delay_struct *mac_delay = &plat->mac_delay;
330 mac_delay->tx_delay /= 290;
331 mac_delay->rx_delay /= 290;
336 struct mac_delay_struct *mac_delay = &plat->mac_delay;
339 mac_delay->tx_delay *= 290;
340 mac_delay->rx_delay *= 290;
345 struct mac_delay_struct *mac_delay = &plat->mac_delay;
350 switch (plat->phy_mode) {
352 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
353 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay);
354 delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv);
356 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
357 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
358 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
361 if (plat->rmii_clk_from_mac) {
362 /* case 1: mac provides the rmii reference clock,
363 * and the clock output to TXC pin.
364 * The egress timing can be adjusted by RMII_TXC delay macro circuit.
365 * The ingress timing can be adjusted by RMII_RXC delay macro circuit.
368 !!mac_delay->tx_delay);
370 mac_delay->tx_delay);
372 mac_delay->tx_inv);
375 !!mac_delay->rx_delay);
377 mac_delay->rx_delay);
379 mac_delay->rx_inv);
381 /* case 2: the rmii reference clock is from external phy,
383 * the reference clk is connected to. The reference clock is a
385 * the reference clock timing adjustment
387 if (plat->rmii_rxc) {
388 /* the rmii reference clock from outside is connected
389 * to RXC pin, the reference clock will be adjusted
390 * by RXC delay macro circuit.
393 !!mac_delay->rx_delay);
395 mac_delay->rx_delay);
397 mac_delay->rx_inv);
399 /* the rmii reference clock from outside is connected
400 * to TXC pin, the reference clock will be adjusted
401 * by TXC delay macro circuit.
404 !!mac_delay->rx_delay);
406 mac_delay->rx_delay);
408 mac_delay->rx_inv);
416 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
417 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay);
418 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv);
420 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
421 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
422 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
426 dev_err(plat->dev, "phy interface not supported\n");
427 return -EINVAL;
430 regmap_update_bits(plat->peri_regmap,
437 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val);
438 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val);
457 struct mac_delay_struct *mac_delay = &plat->mac_delay;
460 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg");
461 if (IS_ERR(plat->peri_regmap)) {
462 dev_err(plat->dev, "Failed to get pericfg syscon\n");
463 return PTR_ERR(plat->peri_regmap);
466 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) {
467 if (tx_delay_ps < plat->variant->tx_delay_max) {
468 mac_delay->tx_delay = tx_delay_ps;
470 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);
471 return -EINVAL;
475 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) {
476 if (rx_delay_ps < plat->variant->rx_delay_max) {
477 mac_delay->rx_delay = rx_delay_ps;
479 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);
480 return -EINVAL;
484 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
485 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
486 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
487 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
488 plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol");
495 const struct mediatek_dwmac_variant *variant = plat->variant;
498 plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL);
499 if (!plat->clks)
500 return -ENOMEM;
502 for (i = 0; i < variant->num_clks; i++)
503 plat->clks[i].id = variant->clk_list[i];
505 ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks);
509 /* The clock labeled as "rmii_internal" is needed only in RMII(when
510 * MAC provides the reference clock), and useless for RGMII/MII or
511 * RMII(when PHY provides the reference clock).
512 * So, "rmii_internal" clock is got and configured only when
513 * reference clock of RMII is from MAC.
515 if (plat->rmii_clk_from_mac) {
516 plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal");
517 if (IS_ERR(plat->rmii_internal_clk))
518 ret = PTR_ERR(plat->rmii_internal_clk);
520 plat->rmii_internal_clk = NULL;
529 const struct mediatek_dwmac_variant *variant = plat->variant;
532 if (variant->dwmac_set_phy_interface) {
533 ret = variant->dwmac_set_phy_interface(plat);
535 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
540 if (variant->dwmac_set_delay) {
541 ret = variant->dwmac_set_delay(plat);
543 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
554 const struct mediatek_dwmac_variant *variant = plat->variant;
558 ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
560 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
564 ret = clk_prepare_enable(plat->rmii_internal_clk);
566 dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret);
570 clk_disable_unprepare(plat->rmii_internal_clk);
571 clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
583 priv_plat->phy_mode = plat->phy_interface;
584 if (priv_plat->mac_wol)
585 plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL;
587 plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
588 plat->riwt_off = 1;
589 plat->maxmtu = ETH_DATA_LEN;
590 plat->host_dma_width = priv_plat->variant->dma_bit_mask;
591 plat->bsp_priv = priv_plat;
592 plat->init = mediatek_dwmac_init;
593 plat->clks_config = mediatek_dwmac_clks_config;
595 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
596 sizeof(*plat->safety_feat_cfg),
598 if (!plat->safety_feat_cfg)
599 return -ENOMEM;
601 plat->safety_feat_cfg->tsoee = 1;
602 plat->safety_feat_cfg->mrxpee = 0;
603 plat->safety_feat_cfg->mestee = 1;
604 plat->safety_feat_cfg->mrxee = 1;
605 plat->safety_feat_cfg->mtxee = 1;
606 plat->safety_feat_cfg->epsi = 0;
607 plat->safety_feat_cfg->edpp = 1;
608 plat->safety_feat_cfg->prtyen = 1;
609 plat->safety_feat_cfg->tmouten = 1;
611 for (i = 0; i < plat->tx_queues_to_use; i++) {
614 plat->tx_queues_cfg[i].tbs_en = 1;
627 priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL);
629 return -ENOMEM;
631 priv_plat->variant = of_device_get_match_data(&pdev->dev);
632 if (!priv_plat->variant) {
633 dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n");
634 return -EINVAL;
637 priv_plat->dev = &pdev->dev;
638 priv_plat->np = pdev->dev.of_node;
663 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
677 struct mediatek_dwmac_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev);
684 { .compatible = "mediatek,mt2712-gmac",
686 { .compatible = "mediatek,mt8195-gmac",
697 .name = "dwmac-mediatek",