Lines Matching +full:serdes +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
56 return func_data->phy_addr; in stmmac_pci_find_phy_addr()
58 return -ENODEV; in stmmac_pci_find_phy_addr()
68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); in serdes_status_poll()
72 } while (--retries); in serdes_status_poll()
74 return -ETIMEDOUT; in serdes_status_poll()
84 if (!intel_priv->mdio_adhoc_addr) in intel_serdes_powerup()
87 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_serdes_powerup()
89 /* Set the serdes rate and the PCLK rate */ in intel_serdes_powerup()
90 data = mdiobus_read(priv->mii, serdes_phy_addr, in intel_serdes_powerup()
96 if (priv->plat->max_speed == 2500) in intel_serdes_powerup()
103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
117 dev_err(priv->device, "Serdes PLL clk request timeout\n"); in intel_serdes_powerup()
122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
133 dev_err(priv->device, "Serdes assert lane reset timeout\n"); in intel_serdes_powerup()
138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
152 dev_err(priv->device, "Serdes power state P0 timeout.\n"); in intel_serdes_powerup()
156 /* PSE only - ungate SGMII PHY Rx Clock */ in intel_serdes_powerup()
157 if (intel_priv->is_pse) in intel_serdes_powerup()
158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, in intel_serdes_powerup()
171 if (!intel_priv->mdio_adhoc_addr) in intel_serdes_powerdown()
174 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_serdes_powerdown()
176 /* PSE only - gate SGMII PHY Rx Clock */ in intel_serdes_powerdown()
177 if (intel_priv->is_pse) in intel_serdes_powerdown()
178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, in intel_serdes_powerdown()
182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
196 dev_err(priv->device, "Serdes power state P3 timeout\n"); in intel_serdes_powerdown()
200 /* de-assert clk_req */ in intel_serdes_powerdown()
201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
205 /* check for clk_ack de-assert */ in intel_serdes_powerdown()
212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); in intel_serdes_powerdown()
216 /* de-assert lane reset */ in intel_serdes_powerdown()
217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
221 /* check for de-assert lane reset reflection */ in intel_serdes_powerdown()
228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); in intel_serdes_powerdown()
240 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_speed_mode_2500()
243 data = mdiobus_read(priv->mii, serdes_phy_addr, in intel_speed_mode_2500()
248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); in intel_speed_mode_2500()
249 priv->plat->max_speed = 2500; in intel_speed_mode_2500()
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX; in intel_speed_mode_2500()
251 priv->plat->mdio_bus_data->default_an_inband = false; in intel_speed_mode_2500()
253 priv->plat->max_speed = 1000; in intel_speed_mode_2500()
265 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; in intel_mgbe_ptp_clk_freq_config()
267 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); in intel_mgbe_ptp_clk_freq_config()
269 if (intel_priv->is_pse) { in intel_mgbe_ptp_clk_freq_config()
279 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); in intel_mgbe_ptp_clk_freq_config()
300 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE); in stmmac_cross_ts_isr()
310 void __iomem *ptpaddr = priv->ptpaddr; in intel_crosststamp()
311 void __iomem *ioaddr = priv->hw->pcsr; in intel_crosststamp()
321 return -EOPNOTSUPP; in intel_crosststamp()
323 intel_priv = priv->plat->bsp_priv; in intel_crosststamp()
328 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) in intel_crosststamp()
329 return -EBUSY; in intel_crosststamp()
331 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
333 mutex_lock(&priv->aux_ts_lock); in intel_crosststamp()
337 switch (priv->plat->int_snapshot_num) { in intel_crosststamp()
351 mutex_unlock(&priv->aux_ts_lock); in intel_crosststamp()
352 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
353 return -EINVAL; in intel_crosststamp()
362 mutex_unlock(&priv->aux_ts_lock); in intel_crosststamp()
374 /* Time sync done Indication - Interrupt method */ in intel_crosststamp()
375 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait, in intel_crosststamp()
378 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
379 return -ETIMEDOUT; in intel_crosststamp()
388 read_lock_irqsave(&priv->ptp_lock, flags); in intel_crosststamp()
391 read_unlock_irqrestore(&priv->ptp_lock, flags); in intel_crosststamp()
392 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); in intel_crosststamp()
393 system->cycles = art_time; in intel_crosststamp()
396 system->cycles *= intel_priv->crossts_adj; in intel_crosststamp()
397 system->cs_id = CSID_X86_ART; in intel_crosststamp()
398 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
414 intel_priv->crossts_adj = art_freq; in intel_mgbe_pse_crossts_adj()
420 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
421 plat->has_gmac = 1; in common_default_data()
422 plat->force_sf_dma_mode = 1; in common_default_data()
424 plat->mdio_bus_data->needs_reset = true; in common_default_data()
427 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
430 plat->unicast_filter_entries = 1; in common_default_data()
433 plat->maxmtu = JUMBO_LEN; in common_default_data()
436 plat->tx_queues_to_use = 1; in common_default_data()
437 plat->rx_queues_to_use = 1; in common_default_data()
440 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
441 plat->rx_queues_cfg[0].use_prio = false; in common_default_data()
444 plat->rx_queues_cfg[0].pkt_route = 0x0; in common_default_data()
450 /* plat->mdio_bus_data->has_xpcs has been set true, so there in intel_mgbe_select_pcs()
454 return &priv->hw->xpcs->pcs; in intel_mgbe_select_pcs()
465 plat->pdev = pdev; in intel_mgbe_common_data()
466 plat->phy_addr = -1; in intel_mgbe_common_data()
467 plat->clk_csr = 5; in intel_mgbe_common_data()
468 plat->has_gmac = 0; in intel_mgbe_common_data()
469 plat->has_gmac4 = 1; in intel_mgbe_common_data()
470 plat->force_sf_dma_mode = 0; in intel_mgbe_common_data()
471 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE); in intel_mgbe_common_data()
482 plat->mult_fact_100ns = 1; in intel_mgbe_common_data()
484 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; in intel_mgbe_common_data()
486 for (i = 0; i < plat->rx_queues_to_use; i++) { in intel_mgbe_common_data()
487 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
488 plat->rx_queues_cfg[i].chan = i; in intel_mgbe_common_data()
491 plat->rx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
494 plat->rx_queues_cfg[i].pkt_route = 0x0; in intel_mgbe_common_data()
497 for (i = 0; i < plat->tx_queues_to_use; i++) { in intel_mgbe_common_data()
498 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
501 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
504 plat->tx_queues_cfg[i].tbs_en = 1; in intel_mgbe_common_data()
508 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; in intel_mgbe_common_data()
509 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; in intel_mgbe_common_data()
511 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; in intel_mgbe_common_data()
512 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
513 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
514 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
515 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
516 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
517 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
518 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
519 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()
521 plat->dma_cfg->pbl = 32; in intel_mgbe_common_data()
522 plat->dma_cfg->pblx8 = true; in intel_mgbe_common_data()
523 plat->dma_cfg->fixed_burst = 0; in intel_mgbe_common_data()
524 plat->dma_cfg->mixed_burst = 0; in intel_mgbe_common_data()
525 plat->dma_cfg->aal = 0; in intel_mgbe_common_data()
526 plat->dma_cfg->dche = true; in intel_mgbe_common_data()
528 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), in intel_mgbe_common_data()
530 if (!plat->axi) in intel_mgbe_common_data()
531 return -ENOMEM; in intel_mgbe_common_data()
533 plat->axi->axi_lpi_en = 0; in intel_mgbe_common_data()
534 plat->axi->axi_xit_frm = 0; in intel_mgbe_common_data()
535 plat->axi->axi_wr_osr_lmt = 1; in intel_mgbe_common_data()
536 plat->axi->axi_rd_osr_lmt = 1; in intel_mgbe_common_data()
537 plat->axi->axi_blen[0] = 4; in intel_mgbe_common_data()
538 plat->axi->axi_blen[1] = 8; in intel_mgbe_common_data()
539 plat->axi->axi_blen[2] = 16; in intel_mgbe_common_data()
541 plat->ptp_max_adj = plat->clk_ptp_rate; in intel_mgbe_common_data()
542 plat->eee_usecs_rate = plat->clk_ptp_rate; in intel_mgbe_common_data()
545 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); in intel_mgbe_common_data()
547 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, in intel_mgbe_common_data()
549 plat->clk_ptp_rate); in intel_mgbe_common_data()
551 if (IS_ERR(plat->stmmac_clk)) { in intel_mgbe_common_data()
552 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); in intel_mgbe_common_data()
553 plat->stmmac_clk = NULL; in intel_mgbe_common_data()
556 ret = clk_prepare_enable(plat->stmmac_clk); in intel_mgbe_common_data()
558 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_mgbe_common_data()
562 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; in intel_mgbe_common_data()
565 plat->multicast_filter_bins = HASH_TABLE_SIZE; in intel_mgbe_common_data()
568 plat->unicast_filter_entries = 1; in intel_mgbe_common_data()
571 plat->maxmtu = JUMBO_LEN; in intel_mgbe_common_data()
573 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN; in intel_mgbe_common_data()
576 plat->vlan_fail_q = plat->rx_queues_to_use - 1; in intel_mgbe_common_data()
578 /* For fixed-link setup, we allow phy-mode setting */ in intel_mgbe_common_data()
579 fwnode = dev_fwnode(&pdev->dev); in intel_mgbe_common_data()
583 /* "phy-mode" setting is optional. If it is set, in intel_mgbe_common_data()
584 * we allow either sgmii or 1000base-x for now. in intel_mgbe_common_data()
590 plat->phy_interface = phy_mode; in intel_mgbe_common_data()
592 dev_warn(&pdev->dev, "Invalid phy-mode\n"); in intel_mgbe_common_data()
596 /* Intel mgbe SGMII interface uses pcs-xcps */ in intel_mgbe_common_data()
597 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || in intel_mgbe_common_data()
598 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { in intel_mgbe_common_data()
599 plat->mdio_bus_data->pcs_mask = BIT(INTEL_MGBE_XPCS_ADDR); in intel_mgbe_common_data()
600 plat->mdio_bus_data->default_an_inband = true; in intel_mgbe_common_data()
601 plat->select_pcs = intel_mgbe_select_pcs; in intel_mgbe_common_data()
604 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ in intel_mgbe_common_data()
605 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; in intel_mgbe_common_data()
606 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; in intel_mgbe_common_data()
608 plat->int_snapshot_num = AUX_SNAPSHOT1; in intel_mgbe_common_data()
610 plat->crosststamp = intel_crosststamp; in intel_mgbe_common_data()
611 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_mgbe_common_data()
614 plat->msi_mac_vec = 29; in intel_mgbe_common_data()
615 plat->msi_lpi_vec = 28; in intel_mgbe_common_data()
616 plat->msi_sfty_ce_vec = 27; in intel_mgbe_common_data()
617 plat->msi_sfty_ue_vec = 26; in intel_mgbe_common_data()
618 plat->msi_rx_base_vec = 0; in intel_mgbe_common_data()
619 plat->msi_tx_base_vec = 1; in intel_mgbe_common_data()
627 plat->rx_queues_to_use = 8; in ehl_common_data()
628 plat->tx_queues_to_use = 8; in ehl_common_data()
629 plat->flags |= STMMAC_FLAG_USE_PHY_WOL; in ehl_common_data()
630 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY; in ehl_common_data()
632 plat->safety_feat_cfg->tsoee = 1; in ehl_common_data()
633 plat->safety_feat_cfg->mrxpee = 1; in ehl_common_data()
634 plat->safety_feat_cfg->mestee = 1; in ehl_common_data()
635 plat->safety_feat_cfg->mrxee = 1; in ehl_common_data()
636 plat->safety_feat_cfg->mtxee = 1; in ehl_common_data()
637 plat->safety_feat_cfg->epsi = 0; in ehl_common_data()
638 plat->safety_feat_cfg->edpp = 0; in ehl_common_data()
639 plat->safety_feat_cfg->prtyen = 0; in ehl_common_data()
640 plat->safety_feat_cfg->tmouten = 0; in ehl_common_data()
648 plat->bus_id = 1; in ehl_sgmii_data()
649 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_sgmii_data()
650 plat->speed_mode_2500 = intel_speed_mode_2500; in ehl_sgmii_data()
651 plat->serdes_powerup = intel_serdes_powerup; in ehl_sgmii_data()
652 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_sgmii_data()
654 plat->clk_ptp_rate = 204800000; in ehl_sgmii_data()
666 plat->bus_id = 1; in ehl_rgmii_data()
667 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; in ehl_rgmii_data()
669 plat->clk_ptp_rate = 204800000; in ehl_rgmii_data()
681 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse0_common_data()
683 intel_priv->is_pse = true; in ehl_pse0_common_data()
684 plat->bus_id = 2; in ehl_pse0_common_data()
685 plat->host_dma_width = 32; in ehl_pse0_common_data()
687 plat->clk_ptp_rate = 200000000; in ehl_pse0_common_data()
697 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse0_rgmii1g_data()
708 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse0_sgmii1g_data()
709 plat->speed_mode_2500 = intel_speed_mode_2500; in ehl_pse0_sgmii1g_data()
710 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse0_sgmii1g_data()
711 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse0_sgmii1g_data()
722 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse1_common_data()
724 intel_priv->is_pse = true; in ehl_pse1_common_data()
725 plat->bus_id = 3; in ehl_pse1_common_data()
726 plat->host_dma_width = 32; in ehl_pse1_common_data()
728 plat->clk_ptp_rate = 200000000; in ehl_pse1_common_data()
738 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse1_rgmii1g_data()
749 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse1_sgmii1g_data()
750 plat->speed_mode_2500 = intel_speed_mode_2500; in ehl_pse1_sgmii1g_data()
751 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse1_sgmii1g_data()
752 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse1_sgmii1g_data()
763 plat->rx_queues_to_use = 6; in tgl_common_data()
764 plat->tx_queues_to_use = 4; in tgl_common_data()
765 plat->clk_ptp_rate = 204800000; in tgl_common_data()
766 plat->speed_mode_2500 = intel_speed_mode_2500; in tgl_common_data()
768 plat->safety_feat_cfg->tsoee = 1; in tgl_common_data()
769 plat->safety_feat_cfg->mrxpee = 0; in tgl_common_data()
770 plat->safety_feat_cfg->mestee = 1; in tgl_common_data()
771 plat->safety_feat_cfg->mrxee = 1; in tgl_common_data()
772 plat->safety_feat_cfg->mtxee = 1; in tgl_common_data()
773 plat->safety_feat_cfg->epsi = 0; in tgl_common_data()
774 plat->safety_feat_cfg->edpp = 0; in tgl_common_data()
775 plat->safety_feat_cfg->prtyen = 0; in tgl_common_data()
776 plat->safety_feat_cfg->tmouten = 0; in tgl_common_data()
784 plat->bus_id = 1; in tgl_sgmii_phy0_data()
785 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_phy0_data()
786 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_phy0_data()
787 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_phy0_data()
798 plat->bus_id = 2; in tgl_sgmii_phy1_data()
799 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_phy1_data()
800 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_phy1_data()
801 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_phy1_data()
812 plat->bus_id = 1; in adls_sgmii_phy0_data()
813 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in adls_sgmii_phy0_data()
815 /* SerDes power up and power down are done in BIOS for ADL */ in adls_sgmii_phy0_data()
827 plat->bus_id = 2; in adls_sgmii_phy1_data()
828 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in adls_sgmii_phy1_data()
830 /* SerDes power up and power down are done in BIOS for ADL */ in adls_sgmii_phy1_data()
880 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
888 "6ES7647-0AA00-0YA2"),
925 plat->bus_id = pci_dev_id(pdev); in quark_default_data()
926 plat->phy_addr = ret; in quark_default_data()
927 plat->phy_interface = PHY_INTERFACE_MODE_RMII; in quark_default_data()
929 plat->dma_cfg->pbl = 16; in quark_default_data()
930 plat->dma_cfg->pblx8 = true; in quark_default_data()
931 plat->dma_cfg->fixed_burst = 1; in quark_default_data()
949 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n", in stmmac_config_single_msi()
954 res->irq = pci_irq_vector(pdev, 0); in stmmac_config_single_msi()
955 res->wol_irq = res->irq; in stmmac_config_single_msi()
956 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; in stmmac_config_single_msi()
957 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n", in stmmac_config_single_msi()
970 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX || in stmmac_config_multi_msi()
971 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) { in stmmac_config_multi_msi()
972 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n", in stmmac_config_multi_msi()
974 return -1; in stmmac_config_multi_msi()
980 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n", in stmmac_config_multi_msi()
986 for (i = 0; i < plat->rx_queues_to_use; i++) { in stmmac_config_multi_msi()
987 res->rx_irq[i] = pci_irq_vector(pdev, in stmmac_config_multi_msi()
988 plat->msi_rx_base_vec + i * 2); in stmmac_config_multi_msi()
992 for (i = 0; i < plat->tx_queues_to_use; i++) { in stmmac_config_multi_msi()
993 res->tx_irq[i] = pci_irq_vector(pdev, in stmmac_config_multi_msi()
994 plat->msi_tx_base_vec + i * 2); in stmmac_config_multi_msi()
997 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
998 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec); in stmmac_config_multi_msi()
999 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1000 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec); in stmmac_config_multi_msi()
1001 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1002 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec); in stmmac_config_multi_msi()
1003 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1004 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec); in stmmac_config_multi_msi()
1005 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1006 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); in stmmac_config_multi_msi()
1008 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; in stmmac_config_multi_msi()
1009 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__); in stmmac_config_multi_msi()
1024 * to take "ownership" of the device or an error code(-ve no) otherwise.
1029 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; in intel_eth_pci_probe()
1035 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); in intel_eth_pci_probe()
1037 return -ENOMEM; in intel_eth_pci_probe()
1039 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); in intel_eth_pci_probe()
1041 return -ENOMEM; in intel_eth_pci_probe()
1043 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
1044 sizeof(*plat->mdio_bus_data), in intel_eth_pci_probe()
1046 if (!plat->mdio_bus_data) in intel_eth_pci_probe()
1047 return -ENOMEM; in intel_eth_pci_probe()
1049 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), in intel_eth_pci_probe()
1051 if (!plat->dma_cfg) in intel_eth_pci_probe()
1052 return -ENOMEM; in intel_eth_pci_probe()
1054 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
1055 sizeof(*plat->safety_feat_cfg), in intel_eth_pci_probe()
1057 if (!plat->safety_feat_cfg) in intel_eth_pci_probe()
1058 return -ENOMEM; in intel_eth_pci_probe()
1063 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", in intel_eth_pci_probe()
1074 plat->bsp_priv = intel_priv; in intel_eth_pci_probe()
1075 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR; in intel_eth_pci_probe()
1076 intel_priv->crossts_adj = 1; in intel_eth_pci_probe()
1082 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1083 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1084 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1085 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1086 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1087 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1088 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1090 ret = info->setup(pdev, plat); in intel_eth_pci_probe()
1097 if (plat->eee_usecs_rate > 0) { in intel_eth_pci_probe()
1100 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; in intel_eth_pci_probe()
1108 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n", in intel_eth_pci_probe()
1114 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); in intel_eth_pci_probe()
1122 clk_disable_unprepare(plat->stmmac_clk); in intel_eth_pci_probe()
1123 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_eth_pci_probe()
1136 struct net_device *ndev = dev_get_drvdata(&pdev->dev); in intel_eth_pci_remove()
1139 stmmac_dvr_remove(&pdev->dev); in intel_eth_pci_remove()
1141 clk_disable_unprepare(priv->plat->stmmac_clk); in intel_eth_pci_remove()
1142 clk_unregister_fixed_rate(priv->plat->stmmac_clk); in intel_eth_pci_remove()
1227 .name = "intel-eth-pci",