Lines Matching +full:probe +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
9 #include <linux/clk-provider.h>
21 #include <linux/reset.h>
37 struct gpio_desc *reset; member
43 struct device *dev = &pdev->dev; in dwc_eth_dwmac_config_dt()
48 if (!plat_dat->axi) { in dwc_eth_dwmac_config_dt()
49 plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL); in dwc_eth_dwmac_config_dt()
51 if (!plat_dat->axi) in dwc_eth_dwmac_config_dt()
52 return -ENOMEM; in dwc_eth_dwmac_config_dt()
55 plat_dat->axi->axi_lpi_en = device_property_read_bool(dev, in dwc_eth_dwmac_config_dt()
56 "snps,en-lpi"); in dwc_eth_dwmac_config_dt()
57 if (device_property_read_u32(dev, "snps,write-requests", in dwc_eth_dwmac_config_dt()
58 &plat_dat->axi->axi_wr_osr_lmt)) { in dwc_eth_dwmac_config_dt()
60 * Since the register has a reset value of 1, if property in dwc_eth_dwmac_config_dt()
63 plat_dat->axi->axi_wr_osr_lmt = 1; in dwc_eth_dwmac_config_dt()
69 plat_dat->axi->axi_wr_osr_lmt--; in dwc_eth_dwmac_config_dt()
72 if (device_property_read_u32(dev, "snps,read-requests", in dwc_eth_dwmac_config_dt()
73 &plat_dat->axi->axi_rd_osr_lmt)) { in dwc_eth_dwmac_config_dt()
75 * Since the register has a reset value of 1, if property in dwc_eth_dwmac_config_dt()
78 plat_dat->axi->axi_rd_osr_lmt = 1; in dwc_eth_dwmac_config_dt()
84 plat_dat->axi->axi_rd_osr_lmt--; in dwc_eth_dwmac_config_dt()
86 device_property_read_u32(dev, "snps,burst-map", &burst_map); in dwc_eth_dwmac_config_dt()
88 /* converts burst-map bitmask to burst array */ in dwc_eth_dwmac_config_dt()
93 plat_dat->axi->axi_blen[a_index] = 4; break; in dwc_eth_dwmac_config_dt()
95 plat_dat->axi->axi_blen[a_index] = 8; break; in dwc_eth_dwmac_config_dt()
97 plat_dat->axi->axi_blen[a_index] = 16; break; in dwc_eth_dwmac_config_dt()
99 plat_dat->axi->axi_blen[a_index] = 32; break; in dwc_eth_dwmac_config_dt()
101 plat_dat->axi->axi_blen[a_index] = 64; break; in dwc_eth_dwmac_config_dt()
103 plat_dat->axi->axi_blen[a_index] = 128; break; in dwc_eth_dwmac_config_dt()
105 plat_dat->axi->axi_blen[a_index] = 256; break; in dwc_eth_dwmac_config_dt()
113 /* dwc-qos needs GMAC4, AAL, TSO and PMT */ in dwc_eth_dwmac_config_dt()
114 plat_dat->has_gmac4 = 1; in dwc_eth_dwmac_config_dt()
115 plat_dat->dma_cfg->aal = 1; in dwc_eth_dwmac_config_dt()
116 plat_dat->flags |= STMMAC_FLAG_TSO_EN; in dwc_eth_dwmac_config_dt()
117 plat_dat->pmt = 1; in dwc_eth_dwmac_config_dt()
128 plat_dat->stmmac_clk = devm_clk_get(&pdev->dev, "apb_pclk"); in dwc_qos_probe()
129 if (IS_ERR(plat_dat->stmmac_clk)) { in dwc_qos_probe()
130 dev_err(&pdev->dev, "apb_pclk clock not found.\n"); in dwc_qos_probe()
131 return PTR_ERR(plat_dat->stmmac_clk); in dwc_qos_probe()
134 err = clk_prepare_enable(plat_dat->stmmac_clk); in dwc_qos_probe()
136 dev_err(&pdev->dev, "failed to enable apb_pclk clock: %d\n", in dwc_qos_probe()
141 plat_dat->pclk = devm_clk_get(&pdev->dev, "phy_ref_clk"); in dwc_qos_probe()
142 if (IS_ERR(plat_dat->pclk)) { in dwc_qos_probe()
143 dev_err(&pdev->dev, "phy_ref_clk clock not found.\n"); in dwc_qos_probe()
144 err = PTR_ERR(plat_dat->pclk); in dwc_qos_probe()
148 err = clk_prepare_enable(plat_dat->pclk); in dwc_qos_probe()
150 dev_err(&pdev->dev, "failed to enable phy_ref clock: %d\n", in dwc_qos_probe()
158 clk_disable_unprepare(plat_dat->stmmac_clk); in dwc_qos_probe()
167 clk_disable_unprepare(priv->plat->pclk); in dwc_qos_remove()
168 clk_disable_unprepare(priv->plat->stmmac_clk); in dwc_qos_remove()
205 dev_err(eqos->dev, "invalid speed %u\n", speed); in tegra_eqos_fix_speed()
211 value = readl(eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
213 writel(value, eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
217 value = readl(eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
219 writel(value, eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
221 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS, in tegra_eqos_fix_speed()
226 dev_err(eqos->dev, "calibration did not start\n"); in tegra_eqos_fix_speed()
230 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS, in tegra_eqos_fix_speed()
235 dev_err(eqos->dev, "calibration didn't finish\n"); in tegra_eqos_fix_speed()
240 value = readl(eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
242 writel(value, eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
244 value = readl(eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
246 writel(value, eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
249 err = clk_set_rate(eqos->clk_tx, rate); in tegra_eqos_fix_speed()
251 dev_err(eqos->dev, "failed to set TX rate: %d\n", err); in tegra_eqos_fix_speed()
260 rate = clk_get_rate(eqos->clk_slave); in tegra_eqos_init()
262 value = (rate / 1000000) - 1; in tegra_eqos_init()
263 writel(value, eqos->regs + GMAC_1US_TIC_COUNTER); in tegra_eqos_init()
272 struct device *dev = &pdev->dev; in tegra_eqos_probe()
276 eqos = devm_kzalloc(&pdev->dev, sizeof(*eqos), GFP_KERNEL); in tegra_eqos_probe()
278 return -ENOMEM; in tegra_eqos_probe()
280 eqos->dev = &pdev->dev; in tegra_eqos_probe()
281 eqos->regs = res->addr; in tegra_eqos_probe()
283 if (!is_of_node(dev->fwnode)) in tegra_eqos_probe()
286 eqos->clk_master = devm_clk_get(&pdev->dev, "master_bus"); in tegra_eqos_probe()
287 if (IS_ERR(eqos->clk_master)) { in tegra_eqos_probe()
288 err = PTR_ERR(eqos->clk_master); in tegra_eqos_probe()
292 err = clk_prepare_enable(eqos->clk_master); in tegra_eqos_probe()
296 eqos->clk_slave = devm_clk_get(&pdev->dev, "slave_bus"); in tegra_eqos_probe()
297 if (IS_ERR(eqos->clk_slave)) { in tegra_eqos_probe()
298 err = PTR_ERR(eqos->clk_slave); in tegra_eqos_probe()
302 data->stmmac_clk = eqos->clk_slave; in tegra_eqos_probe()
304 err = clk_prepare_enable(eqos->clk_slave); in tegra_eqos_probe()
308 eqos->clk_rx = devm_clk_get(&pdev->dev, "rx"); in tegra_eqos_probe()
309 if (IS_ERR(eqos->clk_rx)) { in tegra_eqos_probe()
310 err = PTR_ERR(eqos->clk_rx); in tegra_eqos_probe()
314 err = clk_prepare_enable(eqos->clk_rx); in tegra_eqos_probe()
318 eqos->clk_tx = devm_clk_get(&pdev->dev, "tx"); in tegra_eqos_probe()
319 if (IS_ERR(eqos->clk_tx)) { in tegra_eqos_probe()
320 err = PTR_ERR(eqos->clk_tx); in tegra_eqos_probe()
324 err = clk_prepare_enable(eqos->clk_tx); in tegra_eqos_probe()
328 eqos->reset = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_OUT_HIGH); in tegra_eqos_probe()
329 if (IS_ERR(eqos->reset)) { in tegra_eqos_probe()
330 err = PTR_ERR(eqos->reset); in tegra_eqos_probe()
335 gpiod_set_value(eqos->reset, 0); in tegra_eqos_probe()
337 /* MDIO bus was already reset just above */ in tegra_eqos_probe()
338 data->mdio_bus_data->needs_reset = false; in tegra_eqos_probe()
340 eqos->rst = devm_reset_control_get(&pdev->dev, "eqos"); in tegra_eqos_probe()
341 if (IS_ERR(eqos->rst)) { in tegra_eqos_probe()
342 err = PTR_ERR(eqos->rst); in tegra_eqos_probe()
346 err = reset_control_assert(eqos->rst); in tegra_eqos_probe()
352 err = reset_control_deassert(eqos->rst); in tegra_eqos_probe()
359 data->fix_mac_speed = tegra_eqos_fix_speed; in tegra_eqos_probe()
360 data->init = tegra_eqos_init; in tegra_eqos_probe()
361 data->bsp_priv = eqos; in tegra_eqos_probe()
362 data->flags |= STMMAC_FLAG_SPH_DISABLE; in tegra_eqos_probe()
366 goto reset; in tegra_eqos_probe()
369 reset: in tegra_eqos_probe()
370 reset_control_assert(eqos->rst); in tegra_eqos_probe()
372 gpiod_set_value(eqos->reset, 1); in tegra_eqos_probe()
374 clk_disable_unprepare(eqos->clk_tx); in tegra_eqos_probe()
376 clk_disable_unprepare(eqos->clk_rx); in tegra_eqos_probe()
378 clk_disable_unprepare(eqos->clk_slave); in tegra_eqos_probe()
380 clk_disable_unprepare(eqos->clk_master); in tegra_eqos_probe()
387 struct tegra_eqos *eqos = get_stmmac_bsp_priv(&pdev->dev); in tegra_eqos_remove()
389 reset_control_assert(eqos->rst); in tegra_eqos_remove()
390 gpiod_set_value(eqos->reset, 1); in tegra_eqos_remove()
391 clk_disable_unprepare(eqos->clk_tx); in tegra_eqos_remove()
392 clk_disable_unprepare(eqos->clk_rx); in tegra_eqos_remove()
393 clk_disable_unprepare(eqos->clk_slave); in tegra_eqos_remove()
394 clk_disable_unprepare(eqos->clk_master); in tegra_eqos_remove()
398 int (*probe)(struct platform_device *pdev, member
405 .probe = dwc_qos_probe,
410 .probe = tegra_eqos_probe,
421 data = device_get_match_data(&pdev->dev); in dwc_eth_dwmac_probe()
442 ret = data->probe(pdev, plat_dat, &stmmac_res); in dwc_eth_dwmac_probe()
444 dev_err_probe(&pdev->dev, ret, "failed to probe subdriver\n"); in dwc_eth_dwmac_probe()
452 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in dwc_eth_dwmac_probe()
459 data->remove(pdev); in dwc_eth_dwmac_probe()
466 const struct dwc_eth_dwmac_data *data = device_get_match_data(&pdev->dev); in dwc_eth_dwmac_remove()
468 stmmac_dvr_remove(&pdev->dev); in dwc_eth_dwmac_remove()
470 data->remove(pdev); in dwc_eth_dwmac_remove()
474 { .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
475 { .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data },
481 .probe = dwc_eth_dwmac_probe,
484 .name = "dwc-eth-dwmac",
492 MODULE_DESCRIPTION("Synopsys DWC Ethernet Quality-of-Service v4.10a driver");