1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*------------------------------------------------------------------------
3  . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
21  ---------------------------------------------------------------------------*/
29  * Any 16-bit access is performed with two 8-bit accesses if the hardware
30  * can't do it directly. Most registers are 16-bit so those are mandatory.
55 #include <asm/mach-types.h>
65 #define SMC_IO_SHIFT		(lp->io_shift)
96 #define SMC_IRQ_FLAGS		(-1)	/* from resource */
114 			 (lp)->cfg.pxa_u16_align4)
148 	while (l-- > 0)  in mcf_insw()
155 	while (l-- > 0)  in mcf_outsw()
177 #define SMC_IO_SHIFT		(lp->io_shift)
225 	struct mii_if_info mii;  member
245 	/* on some platforms a u16 write must be 4-bytes aligned */
251 #define SMC_8BIT(p)	((p)->cfg.flags & SMC91X_USE_8BIT)
252 #define SMC_16BIT(p)	((p)->cfg.flags & SMC91X_USE_16BIT)
253 #define SMC_32BIT(p)	((p)->cfg.flags & SMC91X_USE_32BIT)
262 #include <linux/dma-mapping.h>
267 	smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
277 	dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
278 	tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,  in smc_pxa_dma_inpump()
282 		dma_async_issue_pending(lp->dma_chan);  in smc_pxa_dma_inpump()
284 			status = dmaengine_tx_status(lp->dma_chan, cookie,  in smc_pxa_dma_inpump()
289 		dmaengine_terminate_all(lp->dma_chan);  in smc_pxa_dma_inpump()
291 	dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
302 	if (!lp->dma_chan) {  in smc_pxa_dma_insl()
311 		len--;  in smc_pxa_dma_insl()
317 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
318 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
321 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insl()
323 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insl()
336 	smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
345 	if (!lp->dma_chan) {  in smc_pxa_dma_insw()
354 		len--;  in smc_pxa_dma_insw()
360 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
361 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
364 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insw()
366 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insw()
526 #define RPC_DPLX	0x1000	// When 1 PHY is in Full-Duplex Mode
527 #define RPC_ANEG	0x0800	// When 1 PHY is in Auto-Negotiate Mode
551 #define CONFIG_EXT_PHY	0x0200	// 1=external MII, 0=internal Phy
556 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
666 // Management Interface Register (MII)
670 #define MII_MDOE	0x0008 // MII Output Enable
671 #define MII_MCLK	0x0004 // MII Clock, pin MDCLK
672 #define MII_MDI		0x0002 // MII Input, pin MDI
673 #define MII_MDO		0x0001 // MII Output, pin MDO
678 /* ( hi: chip id   low: rev # ) */
739  * Generic PHY registers can be found in <linux/mii.h>
741  * These phy registers are specific to our on-board phy.
763 #define PHY_CFG2_MREG		0x0008	// 1=Multiple register access (MII mgt)
776 #define PHY_INT_SPDDET		0x0080	// 1=100Base-TX mode, 0=10Base-T mode
805  * Note: the following macros do *not* select the bank -- this must
835  * effects and use a 32-bit access.
837  * Enforce it on any 32-bit capable setup for now.
1036 				__len -= 2;				\
1040 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1041 				__ioaddr = lp->datacs;			\
1065 				 * Back both source (on-chip) and	\
1073 				__ptr -= 2;				\
1078 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1079 				__ioaddr = lp->datacs;			\