76 #define SIS_W32(reg, val)	writel ((val), ioaddr + (reg))  macro
369 	SIS_W32(GMIIControl, ctl);  in __mdio_cmd()
426 	SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));  in sis190_read_eeprom()
441 	SIS_W32(IntrMask, 0x00);  in sis190_irq_mask_and_ack()
442 	SIS_W32(IntrStatus, 0xffffffff);  in sis190_irq_mask_and_ack()
450 	SIS_W32(TxControl, 0x1a00);  in sis190_asic_down()
451 	SIS_W32(RxControl, 0x1a00);  in sis190_asic_down()
755 	SIS_W32(IntrStatus, status);  in sis190_irq()
869 	SIS_W32(RxHashTable, mc_filter[0]);  in sis190_set_rx_mode()
870 	SIS_W32(RxHashTable + 4, mc_filter[1]);  in sis190_set_rx_mode()
877 	SIS_W32(IntrControl, 0x8000);  in sis190_soft_reset()
879 	SIS_W32(IntrControl, 0x0);  in sis190_soft_reset()
890 	SIS_W32(TxDescStartAddr, tp->tx_dma);  in sis190_hw_start()
891 	SIS_W32(RxDescStartAddr, tp->rx_dma);  in sis190_hw_start()
893 	SIS_W32(IntrStatus, 0xffffffff);  in sis190_hw_start()
894 	SIS_W32(IntrMask, 0x0);  in sis190_hw_start()
895 	SIS_W32(GMIIControl, 0x0);  in sis190_hw_start()
896 	SIS_W32(TxMacControl, 0x60);  in sis190_hw_start()
898 	SIS_W32(RxHashTable, 0x0);  in sis190_hw_start()
899 	SIS_W32(0x6c, 0x0);  in sis190_hw_start()
900 	SIS_W32(RxWolCtrl, 0x0);  in sis190_hw_start()
901 	SIS_W32(RxWolData, 0x0);  in sis190_hw_start()
908 	SIS_W32(IntrMask, sis190_intr_mask);  in sis190_hw_start()
910 	SIS_W32(TxControl, 0x1a00 | CmdTxEnb);  in sis190_hw_start()
911 	SIS_W32(RxControl, 0x1a1d);  in sis190_hw_start()
1004 		SIS_W32(StationControl, p->ctl);  in sis190_phy_task()
1007 			SIS_W32(RGDelay, 0x0441);  in sis190_phy_task()
1008 			SIS_W32(RGDelay, 0x0440);  in sis190_phy_task()
1240 	SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);  in sis190_start_xmit()
1566 	SIS_W32(IntrMask, 0x0000);  in sis190_tx_timeout()