1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
65  * queues. */
86 #define EFX_RX_USR_BUF_SIZE	(2048 - 256)
89  * of every buffer.  Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111  * struct efx_buffer - A general-purpose DMA buffer
113  * @dma_addr: DMA base address of the buffer
126  * struct efx_tx_buffer - buffer state for a TX descriptor
131  * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
133  * @dma_addr: DMA address of the fragment.
134  * @flags: Flags for allocation and DMA mapping type
138  * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
164  * struct efx_tx_queue - An Efx TX queue
177  * @queue: DMA queue number
179  *	Is our index within @channel->tx_queue array.
187  *	%EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
206  *	only get the up-to-date value of @write_count if this
208  *	avoid cache-line ping-pong between the xmit path and the
237  *	Filled in iff @efx->type->option_descriptors; only used for PIO.
241  *	only get the up-to-date value of read_count if this
243  *	avoid cache-line ping-pong between the xmit path and the
258  *	@read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
321 #define EFX_TX_CB_SIZE	(1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
324  * struct efx_rx_buffer - An Efx RX data buffer
325  * @dma_addr: DMA base address of the buffer
328  * @page_offset: If pending: offset in @page of DMA base address.
330  * @len: If pending: length for DMA descriptor.
350  * struct efx_rx_page_state - Page-based rx buffer state
353  * Used to facilitate sharing dma mappings between recycled rx buffers
356  * @dma_addr: The dma address of this page.
365  * struct efx_rx_queue - An Efx RX queue
384  * @page_ring: The ring to store DMA mapped pages for reuse.
396  * @min_fill: RX descriptor minimum non-zero fill level.
457  * struct efx_channel - An Efx channel
468  * @irq: IRQ number (MSI and MSI-X only)
515  * @tx_queue: TX queues for this channel
589  * struct efx_msi_context - Context for each MSI
604  * struct efx_channel_type - distinguishes traffic and extra channels
616  * @want_txqs: Determine whether this channel should have TX queues
617  *	created.  If %NULL, TX queues are not created.
621  *	channel's TX queues.
650 	STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
659 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
714 /* Pseudo bit-mask flow control field */
720  * struct efx_link_state - Current state of the link
722  * @fd: Link is full-duplex
736 	return left->up == right->up && left->fd == right->fd &&  in efx_link_state_equal()
737 		left->fc == right->fc && left->speed == right->speed;  in efx_link_state_equal()
741  * enum efx_phy_mode - PHY operating mode flags
762  * struct efx_hw_stat_desc - Description of a hardware statistic
765  * @dma_width: Width in bits (0 for non-DMA statistics)
766  * @offset: Offset within stats (ignored for non-DMA statistics)
779  * struct efx_rss_context_priv - driver private data for an RSS context
782  * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
790  * struct efx_rss_context - an RSS context
791  * @priv: hardware-specific state
805 #define EFX_ARFS_FILTER_ID_PENDING	-1
806 #define EFX_ARFS_FILTER_ID_ERROR	-2
807 #define EFX_ARFS_FILTER_ID_REMOVING	-3
809  * struct efx_arfs_rule - record of an ARFS filter and its IDs
811  * @spec: details of the filter (used as key for hash table).  Use efx->type to
832  * struct efx_async_filter_insertion - Request to asynchronously insert a filter
838  * @flow_id: Identifies the kernel-side flow for which this request was made
856 	EFX_XDP_TX_QUEUES_BORROWED	/* queues borrowed from net stack */
862  * struct efx_nic - an Efx NIC
880  * @vi_stride: step between per-VI registers / memory regions
884  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
886  * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
887  * @irq_rx_moderation_us: IRQ moderation time for RX event queues
891  * @tx_queue: TX DMA queues
892  * @rx_queue: RX DMA queues
895  * @extra_channel_types: Types of extra (non-traffic) channels that
899  * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
900  * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
901  * @rxq_entries: Size of receive queues requested by user.
902  * @txq_entries: Size of transmit queues requested by user.
909  * @n_rx_channels: Number of channels used for RX (= number of RX queues)
911  * @n_extra_tx_channels: Number of extra channels with TX queues
912  * @tx_queues_per_channel: number of TX queues probed on each channel
915  * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
916  * @rx_ip_align: RX DMA address offset to have IP header aligned in
918  * @rx_dma_len: Current maximum RX DMA length
928  *	(valid only if channel->sync_timestamps_enabled; always negative)
935  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
940  * @selftest_work: Work item for asynchronous self-test
943  * @mcdi: Management-Controller-to-Driver Interface state
956  * @stats_buffer: DMA buffer for statistics
958  * @phy_data: PHY private data (including PHY-specific stats)
966  * @fc_disable: When non-zero flow control is disabled. Typically used to
967  *	ensure that network back pressure doesn't delay dma queue flushes.
972  * @loopback_selftest: Offline self-test private state
975  * @filter_state: Architecture-dependent filter table state
977  * @rps_slot_map: bitmap of in-flight entries in @rps_slot
983  * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
984  * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
988  *	flush receive queues.
998  * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their
1203  * struct efx_probe_data - State after hardware probe
1217 	return &probe_data->efx;  in efx_netdev_priv()
1222 	return efx->net_dev->reg_state == NETREG_REGISTERED;  in efx_dev_registered()
1227 	return efx->port_num;  in efx_port_num()
1245  * struct efx_nic_type - Efx device type definition
1262  * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1287  *	The SDU length may be any value from 0 up to the protocol-
1300  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
1352  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1363  * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1367  * @print_additional_fwver: Dump NIC-specific additional FW version info
1375  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1376  * @max_dma_mask: Maximum possible DMA mask
1581 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);  in efx_get_channel()
1582 	return efx->channel[index];  in efx_get_channel()
1587 	for (_channel = (_efx)->channel[0];				\
1589 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1590 		     (_efx)->channel[_channel->channel + 1] : NULL)
1594 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1596 	     _channel = _channel->channel ?				\
1597 		     (_efx)->channel[_channel->channel - 1] : NULL)
1602 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);  in efx_get_tx_channel()
1603 	return efx->channel[efx->tx_channel_offset + index];  in efx_get_tx_channel()
1609 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);  in efx_get_xdp_channel()
1610 	return efx->channel[efx->xdp_channel_offset + index];  in efx_get_xdp_channel()
1615 	return channel->channel - channel->efx->xdp_channel_offset <  in efx_channel_is_xdp_tx()
1616 	       channel->efx->n_xdp_channels;  in efx_channel_is_xdp_tx()
1621 	return channel && channel->channel >= channel->efx->tx_channel_offset;  in efx_channel_has_tx_queues()
1627 		return channel->efx->xdp_tx_per_channel;  in efx_channel_num_tx_queues()
1628 	return channel->efx->tx_queues_per_channel;  in efx_channel_num_tx_queues()
1635 	return channel->tx_queue_by_type[type];  in efx_channel_get_tx_queue()
1646 /* Iterate over all TX queues belonging to a channel */
1651 		for (_tx_queue = (_channel)->tx_queue;			\
1652 		     _tx_queue < (_channel)->tx_queue +			\
1658 	return channel->rx_queue.core_index >= 0;  in efx_channel_has_rx_queue()
1665 	return &channel->rx_queue;  in efx_channel_get_rx_queue()
1668 /* Iterate over all RX queues belonging to a channel */
1673 		for (_rx_queue = &(_channel)->rx_queue;			\
1685 	return efx_rx_queue_channel(rx_queue)->channel;  in efx_rx_queue_index()
1694 	return &rx_queue->buffer[index];  in efx_rx_buffer()
1700 	if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))  in efx_rx_buf_next()
1707  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1715  * The 10G MAC requires 8-byte alignment on the frame
1718  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1729 	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;  in efx_xmit_with_hwtstamp()
1733 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;  in efx_xmit_hwtstamp_pending()
1736 /* Get the max fill level of the TX queues on this channel */
1745 				 tx_queue->insert_count - tx_queue->read_count);  in efx_channel_tx_fill_level()
1759 				 tx_queue->insert_count - tx_queue->old_read_count);  in efx_channel_tx_old_fill_level()
1771 	const struct net_device *net_dev = efx->net_dev;  in efx_supported_features()
1773 	return net_dev->features | net_dev->hw_features;  in efx_supported_features()
1780 	return tx_queue->insert_count & tx_queue->ptr_mask;  in efx_tx_queue_get_insert_index()
1787 	return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];  in __efx_tx_queue_get_insert_buffer()
1797 	EFX_WARN_ON_ONCE_PARANOID(buffer->len);  in efx_tx_queue_get_insert_buffer()
1798 	EFX_WARN_ON_ONCE_PARANOID(buffer->flags);  in efx_tx_queue_get_insert_buffer()
1799 	EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);  in efx_tx_queue_get_insert_buffer()