Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
99 "Reducing number of rx queues from %u to %u.\n", in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
111 netif_warn(efx, probe, efx->net_dev, in efx_wanted_parallelism()
113 "VF support. Increase vf-msix-limit to use more " in efx_wanted_parallelism()
140 * we allocate a TX queue per CPU. We share event queues across in efx_allocate_msix_channels()
141 * multiple tx queues, assuming tx and ev queues are both in efx_allocate_msix_channels()
149 vec_count = pci_msix_vec_count(efx->pci_dev); in efx_allocate_msix_channels()
156 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
160 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_allocate_msix_channels()
161 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
164 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
166 } else if (n_channels + n_xdp_tx > efx->max_vis) { in efx_allocate_msix_channels()
167 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_allocate_msix_channels()
168 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
169 "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n", in efx_allocate_msix_channels()
170 n_xdp_tx, n_channels, efx->max_vis); in efx_allocate_msix_channels()
171 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
174 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_SHARED; in efx_allocate_msix_channels()
175 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
179 n_xdp_ev = max_channels - n_channels; in efx_allocate_msix_channels()
180 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
184 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_DEDICATED; in efx_allocate_msix_channels()
187 if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_BORROWED) { in efx_allocate_msix_channels()
188 efx->n_xdp_channels = n_xdp_ev; in efx_allocate_msix_channels()
189 efx->xdp_tx_per_channel = tx_per_ev; in efx_allocate_msix_channels()
190 efx->xdp_tx_queue_count = n_xdp_tx; in efx_allocate_msix_channels()
192 netif_dbg(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
193 "Allocating %d TX and %d event queues for XDP\n", in efx_allocate_msix_channels()
196 efx->n_xdp_channels = 0; in efx_allocate_msix_channels()
197 efx->xdp_tx_per_channel = 0; in efx_allocate_msix_channels()
198 efx->xdp_tx_queue_count = n_xdp_tx; in efx_allocate_msix_channels()
202 netif_err(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
203 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", in efx_allocate_msix_channels()
205 netif_err(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
212 efx->n_channels = n_channels; in efx_allocate_msix_channels()
214 /* Ignore XDP tx channels when creating rx channels. */ in efx_allocate_msix_channels()
215 n_channels -= efx->n_xdp_channels; in efx_allocate_msix_channels()
218 efx->n_tx_channels = in efx_allocate_msix_channels()
220 efx->max_tx_channels); in efx_allocate_msix_channels()
221 efx->tx_channel_offset = in efx_allocate_msix_channels()
222 n_channels - efx->n_tx_channels; in efx_allocate_msix_channels()
223 efx->n_rx_channels = in efx_allocate_msix_channels()
224 max(n_channels - in efx_allocate_msix_channels()
225 efx->n_tx_channels, 1U); in efx_allocate_msix_channels()
227 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); in efx_allocate_msix_channels()
228 efx->tx_channel_offset = 0; in efx_allocate_msix_channels()
229 efx->n_rx_channels = n_channels; in efx_allocate_msix_channels()
232 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); in efx_allocate_msix_channels()
233 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); in efx_allocate_msix_channels()
235 efx->xdp_channel_offset = n_channels; in efx_allocate_msix_channels()
237 netif_dbg(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
238 "Allocating %u RX channels\n", in efx_allocate_msix_channels()
239 efx->n_rx_channels); in efx_allocate_msix_channels()
241 return efx->n_channels; in efx_allocate_msix_channels()
245 * the resulting numbers of channels and RX queues.
255 if (efx->extra_channel_type[i]) in efx_probe_interrupts()
258 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { in efx_probe_interrupts()
263 rc = efx_allocate_msix_channels(efx, efx->max_channels, in efx_probe_interrupts()
269 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, in efx_probe_interrupts()
274 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
275 "could not enable MSI-X\n"); in efx_probe_interrupts()
276 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) in efx_probe_interrupts()
277 efx->interrupt_mode = EFX_INT_MODE_MSI; in efx_probe_interrupts()
281 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
282 "WARNING: Insufficient MSI-X vectors" in efx_probe_interrupts()
284 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
290 for (i = 0; i < efx->n_channels; i++) in efx_probe_interrupts()
291 efx_get_channel(efx, i)->irq = in efx_probe_interrupts()
297 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { in efx_probe_interrupts()
298 efx->n_channels = 1; in efx_probe_interrupts()
299 efx->n_rx_channels = 1; in efx_probe_interrupts()
300 efx->n_tx_channels = 1; in efx_probe_interrupts()
301 efx->tx_channel_offset = 0; in efx_probe_interrupts()
302 efx->n_xdp_channels = 0; in efx_probe_interrupts()
303 efx->xdp_channel_offset = efx->n_channels; in efx_probe_interrupts()
304 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_probe_interrupts()
305 rc = pci_enable_msi(efx->pci_dev); in efx_probe_interrupts()
307 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; in efx_probe_interrupts()
309 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
311 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) in efx_probe_interrupts()
312 efx->interrupt_mode = EFX_INT_MODE_LEGACY; in efx_probe_interrupts()
319 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { in efx_probe_interrupts()
320 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); in efx_probe_interrupts()
321 efx->n_rx_channels = 1; in efx_probe_interrupts()
322 efx->n_tx_channels = 1; in efx_probe_interrupts()
323 efx->tx_channel_offset = efx_separate_tx_channels ? 1 : 0; in efx_probe_interrupts()
324 efx->n_xdp_channels = 0; in efx_probe_interrupts()
325 efx->xdp_channel_offset = efx->n_channels; in efx_probe_interrupts()
326 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_probe_interrupts()
327 efx->legacy_irq = efx->pci_dev->irq; in efx_probe_interrupts()
331 efx->n_extra_tx_channels = 0; in efx_probe_interrupts()
332 j = efx->xdp_channel_offset; in efx_probe_interrupts()
334 if (!efx->extra_channel_type[i]) in efx_probe_interrupts()
336 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { in efx_probe_interrupts()
337 efx->extra_channel_type[i]->handle_no_channel(efx); in efx_probe_interrupts()
339 --j; in efx_probe_interrupts()
340 efx_get_channel(efx, j)->type = in efx_probe_interrupts()
341 efx->extra_channel_type[i]; in efx_probe_interrupts()
343 efx->n_extra_tx_channels++; in efx_probe_interrupts()
347 rss_spread = efx->n_rx_channels; in efx_probe_interrupts()
350 if (efx->type->sriov_wanted) { in efx_probe_interrupts()
351 efx->rss_spread = ((rss_spread > 1 || in efx_probe_interrupts()
352 !efx->type->sriov_wanted(efx)) ? in efx_probe_interrupts()
357 efx->rss_spread = rss_spread; in efx_probe_interrupts()
365 const struct cpumask *numa_mask = cpumask_of_pcibus(efx->pci_dev->bus); in efx_set_interrupt_affinity()
373 cpu = -1; in efx_set_interrupt_affinity()
378 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_set_interrupt_affinity()
387 irq_set_affinity_hint(channel->irq, NULL); in efx_clear_interrupt_affinity()
405 /* Remove MSI/MSI-X interrupts */ in efx_remove_interrupts()
407 channel->irq = 0; in efx_remove_interrupts()
408 pci_disable_msi(efx->pci_dev); in efx_remove_interrupts()
409 pci_disable_msix(efx->pci_dev); in efx_remove_interrupts()
412 efx->legacy_irq = 0; in efx_remove_interrupts()
426 struct efx_nic *efx = channel->efx; in efx_probe_eventq()
429 netif_dbg(efx, probe, efx->net_dev, in efx_probe_eventq()
430 "chan %d create event queue\n", channel->channel); in efx_probe_eventq()
432 /* Build an event queue with room for one event per tx and rx buffer, in efx_probe_eventq()
435 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); in efx_probe_eventq()
437 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; in efx_probe_eventq()
445 struct efx_nic *efx = channel->efx; in efx_init_eventq()
448 EFX_WARN_ON_PARANOID(channel->eventq_init); in efx_init_eventq()
450 netif_dbg(efx, drv, efx->net_dev, in efx_init_eventq()
451 "chan %d init event queue\n", channel->channel); in efx_init_eventq()
455 efx->type->push_irq_moderation(channel); in efx_init_eventq()
456 channel->eventq_read_ptr = 0; in efx_init_eventq()
457 channel->eventq_init = true; in efx_init_eventq()
465 netif_dbg(channel->efx, ifup, channel->efx->net_dev, in efx_start_eventq()
466 "chan %d start event queue\n", channel->channel); in efx_start_eventq()
469 channel->enabled = true; in efx_start_eventq()
472 napi_enable(&channel->napi_str); in efx_start_eventq()
479 if (!channel->enabled) in efx_stop_eventq()
482 napi_disable(&channel->napi_str); in efx_stop_eventq()
483 channel->enabled = false; in efx_stop_eventq()
488 if (!channel->eventq_init) in efx_fini_eventq()
491 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_fini_eventq()
492 "chan %d fini event queue\n", channel->channel); in efx_fini_eventq()
495 channel->eventq_init = false; in efx_fini_eventq()
500 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_remove_eventq()
501 "chan %d remove event queue\n", channel->channel); in efx_remove_eventq()
520 time = jiffies - channel->rfs_last_expiry; in efx_filter_rfs_expire()
521 quota = channel->rfs_filter_count * time / (30 * HZ); in efx_filter_rfs_expire()
522 if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota))) in efx_filter_rfs_expire()
523 channel->rfs_last_expiry += time; in efx_filter_rfs_expire()
541 channel->efx = efx; in efx_alloc_channel()
542 channel->channel = i; in efx_alloc_channel()
543 channel->type = &efx_default_channel_type; in efx_alloc_channel()
546 tx_queue = &channel->tx_queue[j]; in efx_alloc_channel()
547 tx_queue->efx = efx; in efx_alloc_channel()
548 tx_queue->queue = -1; in efx_alloc_channel()
549 tx_queue->label = j; in efx_alloc_channel()
550 tx_queue->channel = channel; in efx_alloc_channel()
554 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); in efx_alloc_channel()
557 rx_queue = &channel->rx_queue; in efx_alloc_channel()
558 rx_queue->efx = efx; in efx_alloc_channel()
559 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); in efx_alloc_channel()
569 efx->channel[i] = efx_alloc_channel(efx, i); in efx_init_channels()
570 if (!efx->channel[i]) in efx_init_channels()
571 return -ENOMEM; in efx_init_channels()
572 efx->msi_context[i].efx = efx; in efx_init_channels()
573 efx->msi_context[i].index = i; in efx_init_channels()
577 efx->interrupt_mode = min(efx->type->min_interrupt_mode, in efx_init_channels()
580 efx->max_channels = EFX_MAX_CHANNELS; in efx_init_channels()
581 efx->max_tx_channels = EFX_MAX_CHANNELS; in efx_init_channels()
591 if (efx->channel[i]) { in efx_fini_channels()
592 kfree(efx->channel[i]); in efx_fini_channels()
593 efx->channel[i] = NULL; in efx_fini_channels()
613 channel->napi_dev = NULL; in efx_copy_channel()
614 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); in efx_copy_channel()
615 channel->napi_str.napi_id = 0; in efx_copy_channel()
616 channel->napi_str.state = 0; in efx_copy_channel()
617 memset(&channel->eventq, 0, sizeof(channel->eventq)); in efx_copy_channel()
620 tx_queue = &channel->tx_queue[j]; in efx_copy_channel()
621 if (tx_queue->channel) in efx_copy_channel()
622 tx_queue->channel = channel; in efx_copy_channel()
623 tx_queue->buffer = NULL; in efx_copy_channel()
624 tx_queue->cb_page = NULL; in efx_copy_channel()
625 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); in efx_copy_channel()
628 rx_queue = &channel->rx_queue; in efx_copy_channel()
629 rx_queue->buffer = NULL; in efx_copy_channel()
630 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); in efx_copy_channel()
631 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); in efx_copy_channel()
633 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); in efx_copy_channel()
645 netif_dbg(channel->efx, probe, channel->efx->net_dev, in efx_probe_channel()
646 "creating channel %d\n", channel->channel); in efx_probe_channel()
648 rc = channel->type->pre_probe(channel); in efx_probe_channel()
668 channel->rx_list = NULL; in efx_probe_channel()
680 struct efx_nic *efx = channel->efx; in efx_get_channel_name()
684 number = channel->channel; in efx_get_channel_name()
686 if (number >= efx->xdp_channel_offset && in efx_get_channel_name()
687 !WARN_ON_ONCE(!efx->n_xdp_channels)) { in efx_get_channel_name()
688 type = "-xdp"; in efx_get_channel_name()
689 number -= efx->xdp_channel_offset; in efx_get_channel_name()
690 } else if (efx->tx_channel_offset == 0) { in efx_get_channel_name()
692 } else if (number < efx->tx_channel_offset) { in efx_get_channel_name()
693 type = "-rx"; in efx_get_channel_name()
695 type = "-tx"; in efx_get_channel_name()
696 number -= efx->tx_channel_offset; in efx_get_channel_name()
698 snprintf(buf, len, "%s%s-%d", efx->name, type, number); in efx_get_channel_name()
706 channel->type->get_name(channel, in efx_set_channel_names()
707 efx->msi_context[channel->channel].name, in efx_set_channel_names()
708 sizeof(efx->msi_context[0].name)); in efx_set_channel_names()
724 netif_err(efx, probe, efx->net_dev, in efx_probe_channels()
726 channel->channel); in efx_probe_channels()
744 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_remove_channel()
745 "destroy chan %d\n", channel->channel); in efx_remove_channel()
752 channel->type->post_remove(channel); in efx_remove_channel()
762 kfree(efx->xdp_tx_queues); in efx_remove_channels()
768 if (xdp_queue_number >= efx->xdp_tx_queue_count) in efx_set_xdp_tx_queue()
769 return -EINVAL; in efx_set_xdp_tx_queue()
771 netif_dbg(efx, drv, efx->net_dev, in efx_set_xdp_tx_queue()
773 tx_queue->channel->channel, tx_queue->label, in efx_set_xdp_tx_queue()
774 xdp_queue_number, tx_queue->queue); in efx_set_xdp_tx_queue()
775 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; in efx_set_xdp_tx_queue()
787 /* We need to mark which channels really have RX and TX in efx_set_xdp_channels()
788 * queues, and adjust the TX queue numbers if we have separate in efx_set_xdp_channels()
789 * RX-only and TX-only channels. in efx_set_xdp_channels()
792 if (channel->channel < efx->tx_channel_offset) in efx_set_xdp_channels()
797 tx_queue->queue = next_queue++; in efx_set_xdp_channels()
805 tx_queue->queue = next_queue++; in efx_set_xdp_channels()
806 netif_dbg(efx, drv, efx->net_dev, in efx_set_xdp_channels()
808 channel->channel, tx_queue->label, in efx_set_xdp_channels()
809 tx_queue->queue); in efx_set_xdp_channels()
817 if (efx->xdp_txq_queues_mode == in efx_set_xdp_channels()
819 tx_queue = &channel->tx_queue[0]; in efx_set_xdp_channels()
827 WARN_ON(efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_DEDICATED && in efx_set_xdp_channels()
828 xdp_queue_number != efx->xdp_tx_queue_count); in efx_set_xdp_channels()
829 WARN_ON(efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED && in efx_set_xdp_channels()
830 xdp_queue_number > efx->xdp_tx_queue_count); in efx_set_xdp_channels()
832 /* If we have more CPUs than assigned XDP TX queues, assign the already in efx_set_xdp_channels()
836 while (xdp_queue_number < efx->xdp_tx_queue_count) { in efx_set_xdp_channels()
837 tx_queue = efx->xdp_tx_queues[next_queue++]; in efx_set_xdp_channels()
848 struct efx_ptp_data *ptp_data = efx->ptp_data; in efx_realloc_channels()
863 for (i = 0; i < efx->n_channels; i++) { in efx_realloc_channels()
864 channel = efx->channel[i]; in efx_realloc_channels()
865 if (channel->type->copy) in efx_realloc_channels()
866 channel = channel->type->copy(channel); in efx_realloc_channels()
868 rc = -ENOMEM; in efx_realloc_channels()
874 /* Swap entry counts and channel pointers */ in efx_realloc_channels()
875 old_rxq_entries = efx->rxq_entries; in efx_realloc_channels()
876 old_txq_entries = efx->txq_entries; in efx_realloc_channels()
877 efx->rxq_entries = rxq_entries; in efx_realloc_channels()
878 efx->txq_entries = txq_entries; in efx_realloc_channels()
879 for (i = 0; i < efx->n_channels; i++) in efx_realloc_channels()
880 swap(efx->channel[i], other_channel[i]); in efx_realloc_channels()
882 for (i = 0; i < efx->n_channels; i++) { in efx_realloc_channels()
883 channel = efx->channel[i]; in efx_realloc_channels()
884 if (!channel->type->copy) in efx_realloc_channels()
889 efx_init_napi_channel(efx->channel[i]); in efx_realloc_channels()
894 efx->ptp_data = NULL; in efx_realloc_channels()
896 for (i = 0; i < efx->n_channels; i++) { in efx_realloc_channels()
898 if (channel && channel->type->copy) { in efx_realloc_channels()
905 efx->ptp_data = ptp_data; in efx_realloc_channels()
909 netif_err(efx, drv, efx->net_dev, in efx_realloc_channels()
919 /* Swap back */ in efx_realloc_channels()
920 efx->rxq_entries = old_rxq_entries; in efx_realloc_channels()
921 efx->txq_entries = old_txq_entries; in efx_realloc_channels()
922 for (i = 0; i < efx->n_channels; i++) in efx_realloc_channels()
923 swap(efx->channel[i], other_channel[i]); in efx_realloc_channels()
933 if (efx->xdp_tx_queue_count) { in efx_set_channels()
934 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); in efx_set_channels()
936 /* Allocate array for XDP TX queue lookup. */ in efx_set_channels()
937 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, in efx_set_channels()
938 sizeof(*efx->xdp_tx_queues), in efx_set_channels()
940 if (!efx->xdp_tx_queues) in efx_set_channels()
941 return -ENOMEM; in efx_set_channels()
945 if (channel->channel < efx->n_rx_channels) in efx_set_channels()
946 channel->rx_queue.core_index = channel->channel; in efx_set_channels()
948 channel->rx_queue.core_index = -1; in efx_set_channels()
953 rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); in efx_set_channels()
956 return netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); in efx_set_channels()
961 return channel->channel - channel->efx->tx_channel_offset < in efx_default_channel_want_txqs()
962 channel->efx->n_tx_channels; in efx_default_channel_want_txqs()
974 BUG_ON(efx->state == STATE_DISABLED); in efx_soft_enable_interrupts()
976 efx->irq_soft_enabled = true; in efx_soft_enable_interrupts()
980 if (!channel->type->keep_eventq) { in efx_soft_enable_interrupts()
997 if (!channel->type->keep_eventq) in efx_soft_enable_interrupts()
1008 if (efx->state == STATE_DISABLED) in efx_soft_disable_interrupts()
1013 efx->irq_soft_enabled = false; in efx_soft_disable_interrupts()
1016 if (efx->legacy_irq) in efx_soft_disable_interrupts()
1017 synchronize_irq(efx->legacy_irq); in efx_soft_disable_interrupts()
1020 if (channel->irq) in efx_soft_disable_interrupts()
1021 synchronize_irq(channel->irq); in efx_soft_disable_interrupts()
1024 if (!channel->type->keep_eventq) in efx_soft_disable_interrupts()
1038 BUG_ON(efx->state == STATE_DISABLED); in efx_enable_interrupts()
1040 if (efx->eeh_disabled_legacy_irq) { in efx_enable_interrupts()
1041 enable_irq(efx->legacy_irq); in efx_enable_interrupts()
1042 efx->eeh_disabled_legacy_irq = false; in efx_enable_interrupts()
1045 efx->type->irq_enable_master(efx); in efx_enable_interrupts()
1048 if (channel->type->keep_eventq) { in efx_enable_interrupts()
1066 if (channel->type->keep_eventq) in efx_enable_interrupts()
1070 efx->type->irq_disable_non_ev(efx); in efx_enable_interrupts()
1082 if (channel->type->keep_eventq) in efx_disable_interrupts()
1086 efx->type->irq_disable_non_ev(efx); in efx_disable_interrupts()
1096 if (channel->type->start) in efx_start_channels()
1097 channel->type->start(channel); in efx_start_channels()
1100 atomic_inc(&efx->active_queues); in efx_start_channels()
1103 /* reset per-queue stats */ in efx_start_channels()
1104 channel->old_n_rx_hw_drops = efx_get_queue_stat_rx_hw_drops(channel); in efx_start_channels()
1105 channel->old_n_rx_hw_drop_overruns = channel->n_rx_nodesc_trunc; in efx_start_channels()
1109 atomic_inc(&efx->active_queues); in efx_start_channels()
1115 WARN_ON(channel->rx_pkt_n_frags); in efx_start_channels()
1126 /* Stop special channels and RX refill. in efx_stop_channels()
1128 * for a sentinel RX to indicate the channel has fully drained. in efx_stop_channels()
1131 if (channel->type->stop) in efx_stop_channels()
1132 channel->type->stop(channel); in efx_stop_channels()
1134 rx_queue->refill_enabled = false; in efx_stop_channels()
1138 /* RX packet processing is pipelined, so wait for the in efx_stop_channels()
1140 * might be kept active by non-data events, so don't in efx_stop_channels()
1150 if (efx->type->fini_dmaq) in efx_stop_channels()
1151 rc = efx->type->fini_dmaq(efx); in efx_stop_channels()
1154 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); in efx_stop_channels()
1156 netif_dbg(efx, drv, efx->net_dev, in efx_stop_channels()
1187 if (unlikely(!channel->enabled)) in efx_process_channel()
1191 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); in efx_process_channel()
1193 channel->rx_list = &rx_list; in efx_process_channel()
1196 tx_queue->pkts_compl = 0; in efx_process_channel()
1197 tx_queue->bytes_compl = 0; in efx_process_channel()
1211 if (tx_queue->bytes_compl) { in efx_process_channel()
1212 netdev_tx_completed_queue(tx_queue->core_txq, in efx_process_channel()
1213 tx_queue->pkts_compl, in efx_process_channel()
1214 tx_queue->bytes_compl); in efx_process_channel()
1216 tx_queue->complete_packets += tx_queue->pkts_compl; in efx_process_channel()
1217 tx_queue->complete_bytes += tx_queue->bytes_compl; in efx_process_channel()
1221 netif_receive_skb_list(channel->rx_list); in efx_process_channel()
1222 channel->rx_list = NULL; in efx_process_channel()
1229 int step = efx->irq_mod_step_us; in efx_update_irq_mod()
1231 if (channel->irq_mod_score < irq_adapt_low_thresh) { in efx_update_irq_mod()
1232 if (channel->irq_moderation_us > step) { in efx_update_irq_mod()
1233 channel->irq_moderation_us -= step; in efx_update_irq_mod()
1234 efx->type->push_irq_moderation(channel); in efx_update_irq_mod()
1236 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { in efx_update_irq_mod()
1237 if (channel->irq_moderation_us < in efx_update_irq_mod()
1238 efx->irq_rx_moderation_us) { in efx_update_irq_mod()
1239 channel->irq_moderation_us += step; in efx_update_irq_mod()
1240 efx->type->push_irq_moderation(channel); in efx_update_irq_mod()
1244 channel->irq_count = 0; in efx_update_irq_mod()
1245 channel->irq_mod_score = 0; in efx_update_irq_mod()
1257 struct efx_nic *efx = channel->efx; in efx_poll()
1263 netif_vdbg(efx, intr, efx->net_dev, in efx_poll()
1265 channel->channel, raw_smp_processor_id()); in efx_poll()
1274 efx->irq_rx_adaptive && in efx_poll()
1275 unlikely(++channel->irq_count == 1000)) { in efx_poll()
1281 time = jiffies - channel->rfs_last_expiry; in efx_poll()
1283 if (channel->rfs_filter_count * time >= 600 * HZ) in efx_poll()
1284 mod_delayed_work(system_wq, &channel->filter_work, 0); in efx_poll()
1301 struct efx_nic *efx = channel->efx; in efx_init_napi_channel()
1303 channel->napi_dev = efx->net_dev; in efx_init_napi_channel()
1304 netif_napi_add(channel->napi_dev, &channel->napi_str, efx_poll); in efx_init_napi_channel()
1317 if (channel->napi_dev) in efx_fini_napi_channel()
1318 netif_napi_del(&channel->napi_str); in efx_fini_napi_channel()
1320 channel->napi_dev = NULL; in efx_fini_napi_channel()